Display panel containing GOA circuits arranged between adjacent rows of pixel units

1. A display panel, comprising a display area and non-display areas positioned at a periphery of the display area, wherein the display area comprises pixel units distributed in an array, and the non-display areas positioned on opposite sides of the display area are provided with a gate driver on array (GOA) bus unit;

two GOA circuit units are arranged side by side between two adjacent rows of the pixel units, and the two GOA circuit units arranged side by side are electrically connected to the pixel units;

the GOA circuit units are electrically connected to the GOA bus unit through signal-connecting lines disposed in the display area; and

wherein the two GOA circuit units arranged side by side share at least one of the signal-connecting lines.

2. The display panel according to claim 1 , wherein the GOA bus unit comprises at least one signal bus extending in a column direction, and each of the signal-connecting lines is correspondingly connected to one of the signal buses.

3. The display panel according to claim 2 , wherein the signal buses comprise a first low-frequency clock signal bus and a second low-frequency clock signal bus, the GOA circuit units are electrically connected to the first low-frequency clock signal bus and the second low-frequency clock signal bus through a first low-frequency clock signal-connecting line and a second low-frequency clock signal-connecting line, respectively, and wherein the two GOA circuit units arranged side by side share at least one of the first low-frequency clock signal-connecting line and the second low-frequency clock signal-connecting line.

4. The display panel according to claim 2 , wherein the signal buses comprise a reset signal bus, and the GOA circuit units are electrically connected to the reset signal bus through a reset signal-connecting line; and wherein the two GOA circuit units arranged side by side share the reset signal-connecting line.

5. The display panel according to claim 2 , wherein the signal buses comprise a power signal bus, and the GOA circuit unit is electrically connected to the power signal bus through a power signal-connecting line; and wherein the two GOA circuit units arranged side by side share the power signal-connecting line.

6. The display panel according to claim 1 , wherein the two GOA circuit units arranged side by side are electrically connected to the pixel units in a same row, alternatively, the two GOA circuit units arranged side by side are electrically connected to two adjacent rows of the pixel units.

7. The display panel according to claim 1 , wherein the two GOA circuit units arranged side by side are a first GOA circuit unit and a second GOA circuit unit, the GOA bus unit comprises a first GOA bus unit and a second GOA bus unit, the first GOA circuit unit is electrically connected to the first GOA bus unit, and the second GOA circuit unit is electrically connected to the second GOA bus unit.

8. The display panel according to claim 7 , wherein one of the first GOA bus unit and the second GOA bus unit comprises the first low-frequency clock signal bus, the other comprises the second low-frequency clock signal bus, one of the first GOA bus unit and the second GOA bus unit comprises the reset signal bus, and the other comprises the power signal bus.

9. The display panel according to claim 8 , wherein a number of the signal buses in the first GOA bus unit and the second GOA bus unit are equal.

10. The display panel according to claim 1 , wherein all the GOA circuit units and the signal-connecting lines are positioned between the two adjacent rows of the pixel units, and the GOA circuit units are electrically connected to the pixel units through a scan line.

11. A display panel, comprising a display area and non-display areas positioned at a periphery of the display area, wherein the display area comprises pixel units distributed in an array, and the non-display areas positioned on opposite sides of the display area are provided with a GOA bus unit, the display panel is a bidirectional driving type display panel, two GOA circuit units are arranged side by side between two adjacent rows of the pixel units, and the two GOA circuit units arranged side by side are electrically connected to the pixel units;

the GOA circuit units are electrically connected to the GOA bus unit through signal-connecting lines disposed in the display area; and

wherein the two GOA circuit units arranged side by side share at least one of the signal-connecting lines.

12. The display panel according to claim 11 , wherein the GOA bus unit comprises at least one signal bus extending in a column direction, and each of the signal-connecting lines is correspondingly connected to one of the signal buses.

13. The display panel according to claim 12 , wherein the signal buses comprise a first low-frequency clock signal bus and a second low-frequency clock signal bus, the GOA circuit units are electrically connected to the first low-frequency clock signal bus and the second low-frequency clock signal bus through a first low-frequency clock signal-connecting line and a second low-frequency clock signal-connecting line, respectively, and wherein the two GOA circuit units arranged side by side share at least one of the first low-frequency clock signal-connecting line and the second low-frequency clock signal-connecting line.

14. The display panel according to claim 12 , wherein the signal buses comprise a reset signal bus, and the GOA circuit units are electrically connected to the reset signal bus through a reset signal-connecting line; and wherein the two GOA circuit units arranged side by side share the reset signal-connecting line.

15. The display panel according to claim 12 , wherein the signal buses comprise a power signal bus, and the GOA circuit units are electrically connected to the power signal bus through a power signal-connecting line; and wherein the two GOA circuit units arranged side by side share the power signal-connecting line.

16. The display panel according to claim 11 , wherein the two GOA circuit units arranged side by side are electrically connected to the pixel units in same row, alternatively, the two GOA circuit units arranged side by side are electrically connected to two adjacent rows of the pixel units.

17. The display panel according to claim 11 , wherein the two GOA circuit units arranged side by side are a first GOA circuit unit and a second GOA circuit unit, the GOA bus unit comprises a first GOA bus unit and a second GOA bus unit, the first GOA circuit units are electrically connected to the first GOA bus unit, and the second GOA circuit units are electrically connected to the second GOA bus unit.

18. The display panel according to claim 17 , wherein one of the first GOA bus unit and the second GOA bus unit comprises the first low-frequency clock signal bus, the other comprises the second low-frequency clock signal bus, one of the first GOA bus unit and the second GOA bus unit comprises the reset signal bus, and the other comprises the power signal bus.

19. The display panel according to claim 18 , wherein a number of the signal buses in the first GOA bus unit and the second GOA bus unit are equal.

20. The display panel according to claim 11 , wherein all the GOA circuit units and the signal-connecting lines are positioned between the two adjacent rows of the pixel units, and the GOA circuit units are electrically connected to the pixel unit through a scan line.