Display device
View Patent ↗A display device is provided, including a circuit board, a display panel, a plurality of clock signal lines, and a plurality of grounding capacitors. The display panel is connected to the circuit board. Each clock signal line extends from the circuit board to the display panel. The plurality of grounding capacitors are disposed on the circuit board. Each grounding capacitor is connected to a corresponding clock signal line.
1. A display device, comprising:
a processor configured to output driving signals and voltages;
a timing controller connected to the processor, and configured to generate control signals based on the driving signals;
a circuit board connected to the timing controller, and configured to generate clock signals according to the voltages and the control signals;
a display panel connected to the circuit board, and comprising a display area and a non-display area; wherein the circuit board is disposed outside the display panel;
a plurality of clock signal lines configured to transmit the clock signals, wherein each of the clock signal lines extends from the circuit board to the non-display area of the display panel;
a gate driver disposed in the non-display area of the display panel, connected to the clock signal lines, and configured to generate gate signals according to the clock signals;
a gate line disposed in the display area of the display panel, connected to the gate driver, and configured to transmit the gate signals; and
a plurality of grounding capacitors disposed on the circuit board, wherein each of the grounding capacitors is connected to a corresponding clock signal line;
wherein each of the clock signal lines comprises a first section and a second section connected to the first section, the first section is disposed on the circuit board, the second section is disposed on the non-display area of the display panel, and each of the grounding capacitors is connected to the first section of a corresponding clock signal line; and
wherein capacitance values of a first subset X of the grounding capacitors connected to a corresponding first subset X of the clock signal lines arranged adjacent to an outer periphery of the display panel are different from capacitance values of a second subset Y of the grounding capacitors connected to a corresponding second subset Y of the clock signal lines arranged adjacent to the display area of the display panel, and the capacitance values of the first subset X of the grounding capacitors connected to the corresponding first subset X of the clock signal lines arranged adjacent to the outer periphery of the display panel are the same as each other.
2. The display device according to claim 1 , wherein the plurality of clock signal lines are arranged in sequence from the display area to the non-display area of the display panel, and capacitance values of two of the grounding capacitors connected to two of the clock signal lines are different from each other.
3. The display device according to claim 1 , wherein the capacitance values of the second subset Y of the grounding capacitors connected to the corresponding second subset Y of the clock signal lines arranged adjacent to the display area of the display panel are the same as each other.
4. The display device according to claim 1 , further comprising a plurality of matching resistors disposed on the circuit board, wherein each of the matching resistors is connected in series with a corresponding clock signal line.
5. The display device according to claim 1 , wherein the circuit board comprises a first circuit board and a second circuit board;
the first section of each clock signal line comprises a first subsection and a second subsection, the first subsection is disposed on the first circuit board, and the second subsection is disposed on the second circuit board;
the second section of each clock signal line comprises a third subsection and a fourth subsection, which are respectively disposed on opposite sides of the display panel;
the gate driver comprises a first gate driver and a second gate driver, the first gate driver is connected to the third subsection, the second gate driver is connected to the fourth subsection, and the first gate driver and the second gate driver are respectively connected to opposite ends of the gate line; and
each of the grounding capacitors comprises a first grounding capacitor and a second grounding capacitor, the first grounding capacitor is disposed on the first circuit board and connected to the first subsection of the corresponding clock signal line, and the second grounding capacitor is disposed on the second circuit board and connected to the second subsection of the corresponding clock signal line.
6. A display device, comprising:
a circuit board;
a display panel connected to the circuit board, and comprising a display area and a non-display area; wherein the circuit board is disposed outside the display panel;
a plurality of clock signal lines configured to transmit clock signals, wherein each of the clock signal lines extends from the circuit board to the non-display area of the display panel;
a gate driver disposed in the non-display area of the display panel, connected to the clock signal lines, and configured to generate gate signals according to the clock signals;
a gate line disposed in the display area of the display panel, connected to the gate driver, and configured to transmit the gate signals; and
a plurality of grounding capacitors disposed on the circuit board, wherein each of the grounding capacitors is connected to a corresponding clock signal line;
wherein each of the clock signal lines comprises a first section and a second section connected to the first section, the first section is disposed on the circuit board, the second section is disposed on the non-display area of the display panel, and each of the grounding capacitors is connected to the first section of a corresponding clock signal line; and
wherein capacitance values of a first subset X of the grounding capacitors connected to a corresponding first subset X of the clock signal lines arranged adjacent to an outer periphery of the display panel are different from capacitance values of a second subset Y of the grounding capacitors connected to a corresponding second subset Y of the clock signal lines arranged adjacent to the display area of the display panel, and the capacitance values of the first subset X of the grounding capacitors connected to the corresponding first subset X of the clock signal lines arranged adjacent to the outer periphery of the display panel are the same as each other.
7. The display device according to claim 6 , wherein the plurality of clock signal lines are arranged in sequence from the display area to the non-display area of the display panel, and capacitance values of two of the grounding capacitors connected to two of the clock signal lines are different from each other.
8. The display device according to claim 6 , wherein the display device comprises a number N of the clock signal lines, and a first clock signal line to an N-th clock signal line are arranged in sequence from the display area to the non-display area of the display panel, a capacitance value of the grounding capacitor connected to the N-th clock signal line is C(N), a capacitance value of the grounding capacitor connected to an (N−1)th clock signal line is C(N−1), and a capacitance value of the grounding capacitor connected to an (N−2)th clock signal line is C(N−2), wherein C(N)≠C(N−1)≠C(N−2).
9. The display device according to claim 8 , wherein the capacitance values of the grounding capacitors connected to the N-th clock signal line, the (N−1)th clock signal line, and the (N−2)th clock signal line gradually decrease in order, such that C(N)<C(N−1)<C(N−2).
10. The display device according to claim 8 , wherein the capacitance values of the grounding capacitors connected to the N-th clock signal line, the (N−1)th clock signal line, and the (N−2)th clock signal line gradually increase in order, such that C(N)>C(N−1)>C(N−2).
11. The display device according to claim 6 , wherein the capacitance values of the second subset Y of the grounding capacitors connected to the corresponding second subset Y of the clock signal lines arranged adjacent to the display area of the display panel are the same as each other.
12. The display device according to claim 6 , wherein the display device comprises a number N of the clock signal lines, a first clock signal line to an N-th clock signal line are arranged in sequence from the display area to the non-display area of the display panel, a capacitance value of the grounding capacitor connected to the first clock signal line is C(1), a capacitance value of the grounding capacitor connected to a second clock signal line is C(2), and a capacitance value of the grounding capacitor connected to a third clock signal line is C(3), wherein C(1)≠C(2)≠C(3).
13. The display device according to claim 6 , wherein-further comprising a plurality of matching resistors disposed on the circuit board, wherein each of the matching resistors is connected in series with a corresponding clock signal line.
14. The display device according to claim 13 , wherein a subset X of the matching resistors, which are connected to the corresponding subset X of the clock signal lines arranged adjacent to the outer periphery of the display panel, have a first resistance value; and
the matching resistors connected to remaining clock signal lines have a second resistance value, and the second resistance value is less than the first resistance value.
15. The display device according to claim 6 , wherein the circuit board comprises a first circuit board and a second circuit board;
the first section of each clock signal line comprises a first subsection and a second subsection, the first subsection is disposed on the first circuit board, and the second subsection is disposed on the second circuit board;
the second section of each clock signal line comprises a third subsection and a fourth subsection, which are respectively disposed on opposite sides of the display panel;
the gate driver comprises a first gate driver and a second gate driver, the first gate driver is connected to the third subsection, the second gate driver is connected to the fourth subsection, and the first gate driver and the second gate driver are respectively connected to opposite ends of the gate line; and
each of the grounding capacitors comprises a first grounding capacitor and a second grounding capacitor, the first grounding capacitor is disposed on the first circuit board and connected to the first subsection of the corresponding clock signal line, and the second grounding capacitor is disposed on the second circuit board and connected to the second subsection of the corresponding clock signal line.
16. The display device according to claim 15 , wherein the first grounding capacitor and the second grounding capacitor connected to a same clock signal line have a same capacitance value.
17. The display device according to claim 15 , wherein the first grounding capacitor and the second grounding capacitor connected to a same clock signal line have different capacitance values.