IP Library Granted Patent US 11,469,308
Granted Patent B2
US 11,469,308 · App. 17/036,592 · Granted Oct 11, 2022

Epitaxial structure of N-face group III nitride, active device, and method for fabricating the same with integration and polarity inversion

Inventor: Chih-Shu Huang (Taipei, TW)
H01L29/475C30B25/183C30B29/406C30B31/22H01L21/8252H01L23/5389H01L27/0605H01L27/0629H01L27/085H01L27/0883H01L29/207H01L29/66462H01L29/778H01L29/7783H01L29/872H01L29/045H01L29/2003H01L29/402H01L29/41766
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Quick Facts
Patent No.
US 11,469,308
App. No.
17/036,592
Granted
Oct 11, 2022
Kind
B2
Abstract

The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-Al y GaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-Al y GaN layer to the junction between the i-GaN channel layer and the i-Al x GaN layer.

Claims (20)

1. A method for fabricating a hybrid enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion using an epitaxial structure of N-face AlGaN/GaN, wherein said epitaxial structure of N-face AlGaN/GaN comprising:

a substrate;

a buffer layer (C-doped) layer on the substrate;

a carbon doped (C-doped) i-GaN layer on the buffer layer (C-doped);

an i-AlyGaN layer, located on said C-doped i-GaN layer;

an i-GaN channel layer, located on said i-AlyGaN layer;

an i-AlxGaN layer, located on said i-GaN channel layer;

a fluorine-ion structure, located in said i-AlxGaN layer; and

a first gate dielectric layer, located on said fluorine-ion structure;

where x=0.1˜0.3 and y=0.05˜0.75,

said method comprising steps of:

implanting fluorine ions into said i-AlxGaN layer (x=0.1˜0.3) using fluorine-ion plasma under a specific electric field (or a specific voltage), and performing a 425° C. thermal treatment for 600 seconds for enabling said fluorine-ion structure to occupy stably a space inside said i-AlxGaN layer;

fabricating said first gate dielectric layer and a second gate dielectric layer;

dividing said epitaxial structure of N-face AlGaN/GaN into a left region and a right region;

in said left region, forming an enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion of GaN and including said fluorine-ion structure for controlling the two-dimensional electron gas below said fluorine-ion structure to be depleted, depositing a passivation dielectric layer with larger compressive stress (dielectric constant n˜1.45) or with larger expansive stress (dielectric constant n˜2.0) and with thickness greater than 200 nanometers, inverting said i-AlxGaN layer/said i-GaN channel layer/said i-AlyGaN layer in a active region of said epitaxial structure of N-face AlGaN/GaN from the N-face polarity to the Ga-face polarity for raising said two-dimensional electron gas from the junction of said i-GaN channel layer/said i-AlyGaN layer to the junction of said i-GaN channel layer/said i-AlxGaN layer; and

in said right region, forming a depletion-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion of GaN, using the stress of said passivation dielectric layer to invert said i-AlxGaN layer/said i-GaN channel layer/said i-AlyGaN layer in the active region of said epitaxial structure of N-face AlGaN/GaN and raise said two-dimensional electron gas from the junction of said i-GaN channel layer/said i-AlyGaN layer to the junction of said i-GaN channel layer/said i-AlxGaN layer, and including said second gate dielectric layer.

2. The method for fabricating a hybrid enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion using said of epitaxial structure of N-face AlGaN/GaN, as recited in claim 1 , further comprising steps of:

using the metal vapor deposition and metal lift-off methods to form a first source electrode and a first drain electrode in said left region and a second source electrode and a second drain electrode in said right region; and

performing a 700˜900° C. thermal treatment for 30 seconds for enabling said first source electrode, said first drain electrode, said second source electrode, and said second drain electrode to become ohmic-contact electrodes.

3. The method for fabricating a hybrid enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion using said epitaxial structure of N-face AlGaN/GaN, as recited in claim 2 , further comprising a step of using the metal vapor deposition and metal lift-off methods to form a first gate electrode, a first source metal interconnect, a first drain metal interconnect, a second source metal interconnect, a second drain metal interconnect, and a second gate electrode; where said first gate electrode is located on said first gate dielectric layer; said first source metal interconnect is located on said first source electrode; said second gate electrode is located on said second gate dielectric layer; and said second drain metal interconnect is located on said second drain electrode.

Priority Claims (1)
TW 106118758 · Jun 6, 2017 · national
Continuity (2)
Continuation 16000057 · Jun 5, 2018
Related Publication 20210013317A1 · Jan 14, 2021