Method for preparing transistor device
The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.
1. A method for preparing a transistor device, comprising:
providing a substrate comprising an isolation structure formed therein;
forming a pair of first trenches extending in a first direction in the isolation structure;
forming a first upper gate and a second upper gate separated from the first upper gate over the substrate, and a pair of first lower gates within the pair of first trenches, wherein the first upper gate, the second upper gate and the pair of the first lower gates are coupled to each other to form a single integral unit; and
forming a source/drain in the substrate at two sides of the first upper gate,
wherein each of the pair of first lower gates extend in the first direction, and the first upper gate and the second upper gate extend in a second direction different from the first direction, wherein the first direction and the second direction are both substantially parallel to an upper surface of the substrate;
wherein the first upper gate includes a length extending in the second direction and a width extending in the first direction, and the length of the first upper gate is greater than the width of the first upper gate.
2. The method of claim 1 , further comprising forming a pair of second trenches extending in the second direction in the isolation structure, wherein the first trenches and the second trenches are coupled to form a frame-like trench.
3. The method of claim 2 , further comprising forming a pair of second lower gates in the pair of second trenches at the same time as the forming of the pair of first lower gates, wherein the first lower gates and the second lower gates are coupled to form a frame-like structure.
4. The method of claim 1 , wherein a depth of the first trenches is between 20 nm and 250 nm.
5. The method of claim 1 , wherein a width of the first trenches is between 15 nm and 100 nm.
6. The method of claim 1 , wherein the forming of the first upper gate and the pair of first lower gates further comprises:
forming a gate dielectric layer and a gate conductive layer over the substrate, wherein a bottom and sidewalls of each first trench are lined by the gate dielectric layer, and the first trenches are filled with the gate conductive layer; and
removing a portion of the gate dielectric layer and a portion of the gate conductive layer to form the first upper gate over the substrate and the first lower gates in the first trenches.
7. The method of claim 1 , further comprising performing an angled halo implant before the forming of the source/drain.
8. The method of claim 7 , wherein the angled halo implant is performed at an angle between 17° and 32°.