Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.
1. A method for producing a 3D memory device, the method comprising:
providing a first level comprising a single crystal layer and control circuits,
wherein said control circuits comprise a plurality of first transistors;
forming at least one second level above said first level;
performing a first etch step comprising etching holes within said second level; and
performing additional processing steps to form a plurality of second transistors and a plurality of first memory cells within said second level,
wherein each second transistor comprises a channel, a source, and a drain all having a same doping type,
wherein each of said plurality of first memory cells comprises at least one of said plurality of second transistors,
wherein said first memory cells are a NAND non-volatile type memory,
wherein said first etch step is followed by a first deposition of a tunneling dielectric and then a second deposition comprising polysilicon,
wherein said control circuits comprise memory peripheral circuits,
wherein at least one of said plurality of first memory cells is disposed at least partially atop a portion of said memory peripheral circuits,
wherein said method of processing at least said memory peripheral circuits accounts for a thermal budget associated with processing said second transistors by adjusting an annealing of said first transistors accordingly; and
wherein said first memory cells comprise charge trap, junction-less transistors.
2. The method according to claim 1 ,
wherein said second level comprises at least two overlying layers comprising different materials.
3. The method according to claim 1 , further comprising:
forming at least one third level above said at least one second level; and
performing a second etch step comprising etching holes within said third level.
4. The method according to claim 1 ,
wherein fabrication processing of said first transistors accounts for a temperature and time associated with said processing said second level and said second transistors by adjusting a process thermal budget of said first level accordingly.
5. The method according to claim 1 ,
wherein said first deposition and/or said second deposition comprises use of Atomic Layer Deposition (“ALD”).
6. The method according to claim 1 ,
wherein said first etch step comprises use of a Reactive Ion Etching (“RIE”) process.
7. A method for producing a 3D memory device, the method comprising:
providing a first level comprising a single crystal layer and control circuits,
wherein said control circuits comprise a plurality of first transistors;
forming at least one second level above said first level;
performing a first etch step comprising etching holes within said second level; and
performing additional processing steps to form a plurality of second transistors and a plurality of first memory cells within said second level,
wherein each second transistor comprises a channel, a source, and a drain all having a same doping type,
wherein each of said plurality of first memory cells comprises at least one of said plurality of second transistors,
wherein said first memory cells are a NAND nonvolatile type memory,
wherein said control circuits comprise memory peripheral circuits,
wherein at least one of said plurality of first memory cells is disposed at least partially atop a portion of said memory peripheral circuits,
wherein fabrication processing of said first transistors accounts for a temperature and time associated with said processing said second level and said second transistors by adjusting a process thermal budget of said first level accordingly; and
wherein said first memory cells comprise charge trap, junction-less transistors.
8. The method according to claim 7 ,
wherein said second level comprises at least two overlying layers comprising different materials.
9. The method according to claim 7 , further comprising:
forming at least one third level above said at least one second level; and
performing a second etch step comprising etching holes within said third level.
10. The method according to claim 7 ,
wherein said first etch step is followed by a first deposition of a tunneling dielectric and then a second deposition comprising polysilicon.
11. The method according to claim 7 ,
wherein said first deposition and/or said second deposition comprises use of Atomic Layer Deposition (“ALD”).
12. The method according to claim 7 ,
wherein said second level comprises a plurality of sub-levels, and
wherein each of said sub-levels comprises a plurality of sub-level memory cells.
13. A method for producing a 3D memory device, the method comprising:
providing a first level comprising a single crystal layer and control circuits,
wherein said control circuits comprise a plurality of first transistors;
forming at least one second level above said first level;
performing a first etch step comprising etching holes within said second level;
performing additional processing steps to form a plurality of second transistors and a plurality of first memory cells within said second level,
wherein each of said first memory cells comprise at least one of said plurality of second transistors,
wherein said control circuits comprise memory peripheral circuits,
wherein at least one of said first memory cells is disposed at least partially atop a portion of said memory peripheral circuits,
wherein fabrication processing of said first transistors accounts for a temperature and time associated with said processing said second level and said plurality of second transistors by adjusting a process thermal budget of said first level accordingly; and
wherein said first memory cells comprise charge trap, junction-less transistors.
14. The method according to claim 13 ,
wherein said second level comprises at least two overlying layers comprising different materials.
15. The method according to claim 13 , further comprising:
forming at least one third level above said at least one second level; and
performing a second etch step comprising etching holes within said third level.
16. The method according to claim 13 ,
wherein said plurality of second transistors each comprise a channel, a source, and a drain having a same doping type, and
wherein said first memory cells are a NAND nonvolatile type memory.
17. The method according to claim 13 ,
wherein said second level comprises a plurality of sub-levels, and
wherein each of said sub-levels comprise a plurality of sub-level memory cells.