IP Library › Granted Patent US 11,495,686
Granted Patent B2
US 11,495,686 · App. 17/147,468 · Granted Nov 8, 2022

Semiconductor device and method for fabricating the same

Inventors: Chi-Hsuan Tang (Kaohsiung, TW); Chung-Ting Huang (Kaohsiung, TW); Bo-Shiun Chen (Taichung, TW); Chun-Jen Chen (Tainan, TW); Yu-Shu Lin (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7848H01L21/0245H01L29/0657H01L29/6656H01L29/66553
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,495,686
App. No.
17/147,468
Granted
Nov 8, 2022
Kind
B2
Abstract

A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.

Claims (32)

1. A method for fabricating a semiconductor device, comprising:

forming a gate structure on a substrate;

forming an epitaxial layer adjacent to the gate structure; and

injecting a precursor and a reacting gas without any germanium-containing gas to directly form a first cap layer comprising a V-shape on the epitaxial layer, wherein a top surface of the first cap layer comprises the V-shape and a bottom surface of the first cap layer comprises a planar surface higher than a top surface of the substrate.

2. The method of claim 1 , further comprising:

forming a spacer adjacent to the gate structure; and

forming the epitaxial layer adjacent to the spacer.

3. The method of claim 1 , wherein the epitaxial layer comprises a second cap layer and the first cap layer is on the second cap layer.

4. The method of claim 3 , wherein a top surface of the second cap layer is higher than a top surface of the substrate.

5. The method of claim 3 , wherein a bottom surface of the second cap layer is even with a top surface of substrate.

6. The method of claim 3 , wherein the first cap layer and the second cap layer comprise different materials.

7. The method of claim 3 , wherein the epitaxial layer and the first cap layer comprise different materials.

8. The method of claim 1 , wherein a bottom surface of the first cap layer is higher than a top surface of the substrate.

9. The method of claim 1 , wherein a top surface of the first cap layer is higher than half the height of the gate structure.

10. A semiconductor device, comprising:

a gate structure on a substrate;

an epitaxial layer adjacent to the gate structure; and

a first cap layer on the epitaxial layer, wherein a top surface of the first cap layer comprises a V-shape and two planar surfaces connected to two sides of the V-shape and a bottom surface of the first cap layer comprises a planar surface higher than a top surface of the substrate.

11. The semiconductor device of claim 10 , further comprising:

a spacer adjacent to the gate structure; and

the epitaxial layer adjacent to the spacer.

12. The semiconductor device of claim 10 , wherein the epitaxial layer comprises a second cap layer, and the first cap layer is on the second cap layer.

13. The semiconductor device of claim 12 , wherein a top surface of the second cap layer is higher than a top surface of the substrate.

14. The semiconductor device of claim 12 , wherein a bottom surface of the second cap layer is even with a top surface of substrate.

15. The semiconductor device of claim 12 , wherein the first cap layer and the second cap layer comprise different materials.

16. The semiconductor device of claim 10 , wherein the epitaxial layer and the first cap layer comprise different materials.

17. The semiconductor device of claim 10 , wherein a bottom surface of the first cap layer is higher than a top surface of the substrate.

18. The semiconductor device of claim 10 , wherein a top surface of the first cap layer is higher than half the height of the gate structure.

19. A semiconductor device, comprising:

a gate structure on a substrate;

an epitaxial layer adjacent to the gate structure; and

a first cap layer on the epitaxial layer, wherein a top surface of the first cap layer comprises a curve concave upward and a bottom surface of the first cap layer comprises a planar surface higher than a top surface of the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2021
From: TANG, CHI-HSUAN; HUANG, CHUNG-TING; CHEN, BO-SHIUN; CHEN, CHUN-JEN; LIN, YU-SHU
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 054898/0099 →
Priority Claims (1)
CN 202011478662.1 · Dec 15, 2020 · national
Continuity (1)
Related Publication 20220190160A1 · Jun 16, 2022
Cited By (1)
US 12,237,415