IP Library › Granted Patent US 12,237,415
Granted Patent B2
US 12,237,415 · App. 18/234,889 · Granted Feb 25, 2025

Method for fabricating semiconductor device

Inventors: Chi-Hsuan Tang (Kaohsiung, TW); Chung-Ting Huang (Kaohsiung, TW); Bo-Shiun Chen (Taichung, TW); Chun-Jen Chen (Tainan, TW); Yu-Shu Lin (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7848H01L21/0245H01L29/0657H01L29/66553H01L29/6656
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Quick Facts
Patent No.
US 12,237,415
App. No.
18/234,889
Granted
Feb 25, 2025
Kind
B2
Abstract

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

Claims (14)

1. A semiconductor device, comprising:

a gate structure on a substrate;

an epitaxial layer adjacent to the gate structure;

a first cap layer on the epitaxial layer, wherein a top surface of the first cap layer comprises a V-shape and two planar surfaces connected to two sides of the V-shape and a bottom surface of the first cap layer comprises a planar surface higher than a top surface of the substrate; and

a contact etch stop layer (CESL) adjacent to the gate structure and on the first cap layer.

2. The semiconductor device of claim 1 , further comprising:

a spacer adjacent to the gate structure; and

the epitaxial layer adjacent to the spacer.

3. The semiconductor device of claim 1 , wherein the epitaxial layer comprises a second cap layer, and the first cap layer is on the second cap layer.

4. The semiconductor device of claim 3 , wherein a top surface of the second cap layer is higher than a top surface of the substrate.

5. The semiconductor device of claim 3 , wherein a bottom surface of the second cap layer is even with a top surface of substrate.

6. The semiconductor device of claim 3 , wherein the first cap layer and the second cap layer comprise different materials.

7. The semiconductor device of claim 1 , wherein the epitaxial layer and the first cap layer comprise different materials.

8. The semiconductor device of claim 1 , wherein a top surface of the first cap layer is higher than half the height of the gate structure.

Priority Claims (1)
CN 202011478662.1 · Dec 15, 2020 · national
Continuity (3)
Continuation 17956840 · Sep 30, 2022
Continuation 17147468 · Jan 13, 2021
Related Publication 20230395719A1 · Dec 7, 2023
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