IP Library › Granted Patent US 11,502,008
Granted Patent B2
US 11,502,008 · App. 16/612,618 · Granted Nov 15, 2022

Dual strip backside metallization for improved alt-FLI plating, KOZ minimization, test enhancement and warpage control

Inventors: Nicholas S. Haehn (Scottsdale, AZ); Edvin Cetegen (Chandler, AZ); Shankar Devasenathipathy (Tempe, AZ)
Assignee: Intel Corporation
H01L23/10H01L21/4846H01L23/538H01L23/585H01L24/13H01L25/0655H01L2224/13147
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Quick Facts
Patent No.
US 11,502,008
App. No.
16/612,618
Granted
Nov 15, 2022
Kind
B2
Abstract

An integrated circuit assembly including a substrate having a surface including at least one area including contact points operable for connection with an integrated circuit die; and at least one ring surrounding the at least one area, the at least one ring including an electrically conductive material. A method of forming an integrated circuit assembly including forming a plurality of electrically conductive rings around a periphery of a die area of a substrate selected for attachment of at least one integrated circuit die, wherein the plurality of rings are formed one inside the other; and forming a plurality of contact points in the die area.

Claims (21)

1. An integrated circuit assembly comprising:

a substrate having a surface comprising at least one area comprising contact points, wherein the contact points have a first height;

a die coupled to the at least one area of the surface of the substrate, the die having an uppermost surface; and

a first ring and a second ring surrounding the at least one area, the second ring surrounding the first ring, and the first ring and the second ring comprising an electrically conductive material, wherein the first ring and the second ring have a second height, the second height the same as the first height, wherein a lateral thickness of the conductive material of the second ring is greater than a lateral thickness of the conductive material of the first ring, and wherein the first ring and the second ring each have an uppermost surface below the uppermost surface of the die.

2. The assembly of claim 1 , wherein the electrically conductive material of the first ring and of the second ring is the same as a material of the contact points.

3. The assembly of claim 2 , wherein the electrically conductive material is copper.

4. The assembly of claim 3 , wherein the contact points comprise plated bumps.

5. The assembly of claim 1 , wherein the at least one area of the surface of the substrate comprises a plurality of areas.

6. The assembly of claim 1 , wherein the contact points comprise plated bumps and a distance from an edge of the die and a nearest point on the at least one ring is selected to effect a uniformity of the plated bumps.

7. An integrated circuit assembly comprising:

a first die coupled to a first area of a surface of a substrate and a second die coupled to a second area of the surface, wherein the first die and the second die are each coupled to contact points on the substrate, and wherein the contact points have a first height, the first die having an uppermost surface, and the second die having an uppermost surface; and

a first ring and a second ring coupled to the substrate and surrounding each of the first die and the second die, the second ring surrounding the first ring, and the first ring and the second ring comprising an electrically conductive material, wherein the first ring and the second ring have a second height, the second height the same as the first height, wherein a lateral thickness of the conductive material of the second ring is greater than a lateral thickness of the conductive material of the first ring, and wherein the first ring and the second ring each have an uppermost surface below the uppermost surface of first die and below the uppermost surface of second die.

8. The assembly of claim 7 , wherein a material of the contact points is similar to the electrically conductive material of the first ring and the second ring.

9. The assembly of claim 8 , wherein the material is copper.

10. The assembly of claim 9 , wherein the contact points comprise plated bumps.

11. A method of forming an integrated circuit assembly comprising:

forming a plurality of electrically conductive rings around a periphery of a die area of a substrate, wherein the plurality of electrically conductive rings has a first height and comprises an electrically conductive material, wherein the plurality of electrically conductive rings comprises a first ring and a second ring, the second ring surrounding the first ring, and wherein a lateral thickness of the conductive material of the second ring is greater than a lateral thickness of the conductive material of the first ring;

forming a plurality of contact points in the die area, wherein the plurality of contact points have a second height, the second height the same as the first height, and

coupling a die to the die area of the substrate, the die having an uppermost surface, wherein the first ring and the second ring each have an uppermost surface below the uppermost surface of the die.

12. The method of claim 11 , wherein the plurality of electrically conductive rings and the plurality of contact points are formed in a similar process operation.

13. The method of claim 12 , wherein the electrically conductive material of the plurality of electrically conductive rings and a material of the plurality of contact points is copper.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2022
From: HAEHN, NICHOLAS S.; CETEGEN, EDVIN; DEVASENATHIPATHY, SHANKAR
To: INTEL CORPORATION
Reel/Frame 060763/0042 →
Continuity (1)
Related Publication 20200203240A1 · Jun 25, 2020