IP Library › Granted Patent US 11,502,057
Granted Patent B2
US 11,502,057 · App. 17/005,186 · Granted Nov 15, 2022

Semiconductor device and manufacturing method thereof

Inventor: Soichi Homma (Yokkaichi Mie, JP)
Assignee: KIOXIA CORPORATION
H01L24/92H01L21/563H01L24/11H01L24/13H01L24/16H01L24/27H01L24/32H01L24/33H01L24/48H01L24/73H01L24/81H01L24/83H01L25/18H01L2224/1146H01L2224/11831H01L2224/11849H01L2224/11912H01L2224/13147H01L2224/13582H01L2224/13611H01L2224/13639H01L2224/13655H01L2224/16227H01L2224/27831H01L2224/32145H01L2224/32225H01L2224/33106H01L2224/33181H01L2224/48145H01L2224/48225H01L2224/73204H01L2224/73215H01L2224/73253H01L2224/73265H01L2224/81191H01L2224/8392H01L2224/83191H01L2224/83192H01L2224/92143
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,502,057
App. No.
17/005,186
Granted
Nov 15, 2022
Kind
B2
Abstract

A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip.

Claims (37)

1. A semiconductor device, comprising:

a substrate having a plurality of pads on a surface of the substrate;

a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate;

a first resin layer between the surface of the substrate and the semiconductor chip;

a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps; and

a third resin layer on the substrate and above the semiconductor chip.

2. The semiconductor device according to claim 1 , wherein the metal bumps are on a first surface of the semiconductor chip that faces the substrate.

3. The semiconductor device according to claim 1 , wherein the pads are electrically connected to wires in the substrate.

4. The semiconductor device according to claim 1 , wherein the first and second resin layers include fillers, and a concentration of filler in the second resin layer is greater than a concentration of filler in the first resin layer.

5. The semiconductor device according to claim 1 , wherein a thermal expansion coefficient of the second resin layer is smaller than a thermal expansion coefficient of the first resin layer.

6. The semiconductor device according to claim 1 , wherein an elastic modulus of the second resin layer is larger than an elastic modulus of the first resin layer.

7. The semiconductor device according to claim 1 , wherein the second resin layer covers a part of a side surface of the semiconductor chip and a side surface of at least one of the metal bumps of the plurality of metal bumps.

8. The semiconductor device according to claim 7 , further comprising:

a first insulating material on the substate, wherein

the second resin layer further covers a part of the first insulating material.

9. A manufacturing method of a semiconductor device, comprising:

forming a first resin layer on a semiconductor chip including a metal bump;

aligning the metal bump with a pad on a substrate, and then bonding the first resin layer to a surface of the substrate;

forming a second resin layer between the substrate and the semiconductor chip, the second resin layer including a reducing agent;

heating the substrate and the semiconductor chip such that the metal bump and the pad are connected to each other; and

curing the second resin layer and forming a third resin layer on the substrate and above the semiconductor chip.

10. The manufacturing method according to claim 9 , wherein the first resin layer is photosensitive and patterned using a lithography technique.

11. The manufacturing method according to claim 9 , further comprising:

heating the substrate and the semiconductor chip before forming the second resin layer.

12. The manufacturing method according to claim 11 , wherein the heating before forming the second resin layer, the forming thereof, and the heating thereafter are performed in an uninterrupted series of steps and without exposing the substrate to ambient atmosphere.

13. The manufacturing method according to claim 9 , wherein the heating includes connecting the metal bump and the pad by flip-chip connection.

14. A manufacturing method of a semiconductor device, comprising:

forming a first resin layer on a substrate, the substrate including a pad;

aligning a metal bump of a semiconductor chip with the pad, and bonding the first resin layer to the semiconductor chip;

forming a second resin layer between the substrate and the semiconductor chip, the second resin layer including a reducing agent;

heating the substrate and the semiconductor chip such that the metal bump and the pad are connected to each other; and

curing the second resin layer and forming a third resin layer on the substrate and above the semiconductor chip.

15. The manufacturing method according to claim 14 , wherein the first resin layer is photosensitive and formed using a lithography technique.

16. The manufacturing method according to claim 14 , further comprising:

heating the substrate and the semiconductor chip before forming the second resin layer.

17. The manufacturing method according to claim 16 , wherein the heating before forming the second resin layer, the forming thereof, and the heating thereafter are performed in an uninterrupted series of steps and without exposing the substrate to ambient atmosphere.

18. The manufacturing method according to claim 14 , wherein the heating includes connecting the metal bump and the pad by flip-chip connection.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2020
From: HOMMA, SOICHI
To: KIOXIA CORPORATION
Reel/Frame 054369/0393 →
Priority Claims (1)
JP JP2020-024557 · Feb 17, 2020 · national
Continuity (1)
Related Publication 20210257332A1 · Aug 19, 2021
Cited By (1)
US 12,431,439