Semiconductor device and method
In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
1. A device comprising:
a channel region;
an interface layer on the channel region;
a gate dielectric layer on the interface layer, the gate dielectric layer having a first surface facing towards the interface layer and a second surface opposite the first surface, the gate dielectric layer having a first concentration of a dipole-inducing element at the first surface, the gate dielectric layer having a second concentration of the dipole-inducing element at the second surface, the second concentration being less than the first concentration;
a capping layer on the gate dielectric layer; and
a gate electrode on the capping layer.
2. The device of claim 1 further comprising:
a first fin extending from a substrate, the first fin comprising the channel region.
3. The device of claim 1 , wherein the dipole-inducing element is lanthanum.
4. The device of claim 1 , wherein the capping layer comprises TiSiN.
5. The device of claim 1 , wherein the second concentration is zero.
6. The device of claim 1 , wherein the capping layer has a third surface facing towards the gate dielectric layer and a fourth surface opposite the third surface, the capping layer having a third concentration of the dipole-inducing element at the third surface, the capping layer having a fourth concentration of the dipole-inducing element at the fourth surface, the fourth concentration being less than the third concentration, the third concentration being less than the first concentration.
7. A device comprising:
a first transistor comprising:
a first channel region;
a first interface layer on the first channel region;
a first gate dielectric layer on the first interface layer, a first interface of the first gate dielectric layer and the first interface layer having a first concentration of a dipole-inducing element;
a first capping layer on the first gate dielectric layer, a second interface of the first capping layer and the first gate dielectric layer being free from the dipole-inducing element; and
a first gate electrode on the first capping layer; and
a second transistor comprising:
a second channel region;
a second interface layer on the second channel region;
a second gate dielectric layer on the second interface layer, a third interface of the second gate dielectric layer and the second interface layer having a second concentration of the dipole-inducing element, the second concentration being different from the first concentration;
a second capping layer on the second gate dielectric layer, a fourth interface of the second capping layer and the second gate dielectric layer being free from the dipole-inducing element; and
a second gate electrode on the second capping layer.
8. The device of claim 7 further comprising:
a first fin extending from a substrate, the first fin comprising the first channel region and the second channel region.
9. The device of claim 7 further comprising:
a first fin extending from a substrate, the first fin comprising the first channel region; and
a second fin extending from the substrate, the second fin comprising the second channel region.
10. The device of claim 7 , wherein the dipole-inducing element is lanthanum.
11. The device of claim 7 , wherein the first capping layer and the second capping layer each comprise TiSiN.
12. The device of claim 7 , wherein the first transistor and the second transistor have different threshold voltages.
13. A device comprising:
a first transistor comprising:
a first channel region;
a first interface layer on the first channel region, the first interface layer being doped with a dipole-inducing element, a first concentration of the dipole-inducing element in the first interface layer increasing in a first direction, the first direction extending away from the first channel region;
a first gate dielectric layer on the first interface layer, the first gate dielectric layer being doped with the dipole-inducing element, a second concentration of the dipole-inducing element in the first gate dielectric layer decreasing in the first direction; and
a first gate electrode on the first gate dielectric layer; and
a second transistor comprising:
a second channel region;
a second interface layer on the second channel region, the second interface layer being free from the dipole-inducing element;
a second gate dielectric layer on the second interface layer, the second gate dielectric layer being free from the dipole-inducing element; and
a second gate electrode on the second gate dielectric layer.
14. The device of claim 13 further comprising:
a first fin extending from a substrate, the first fin comprising the first channel region and the second channel region.
15. The device of claim 13 further comprising:
a first fin extending from a substrate, the first fin comprising the first channel region; and
a second fin extending from the substrate, the second fin comprising the second channel region.
16. The device of claim 13 , wherein the dipole-inducing element is lanthanum.
17. The device of claim 13 , wherein the first transistor further comprises a first capping layer between the first gate dielectric layer and the first gate electrode, the first capping layer being doped with the dipole-inducing element, and wherein the second transistor further comprises a second capping layer between the second gate dielectric layer and the second gate electrode, the second capping layer being free from the dipole-inducing element.
18. The device of claim 17 , wherein a third concentration of the dipole-inducing element in the first capping layer decreases in the first direction.
19. The device of claim 17 , wherein the first capping layer and the second capping layer each comprise TiSiN.
20. The device of claim 13 , wherein the first transistor and the second transistor have different threshold voltages.