Gate structures in semiconductor devices
A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.
1 . A semiconductor device, comprising:
a first gate structure comprising:
a first interfacial oxide (IL) layer;
a first high-K (HK) dielectric layer disposed on the first IL layer, wherein the HK dielectric layer comprises a rare-earth metal dopant or an alkaline metal dopant; and
a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer; and
a second gate structure comprising:
a second IL layer,
a second HK dielectric layer disposed on the second IL layer, wherein the second HK dielectric layer comprises:
a transition metal dopant, and
the rare-earth metal dopant or the alkaline metal dopant,
wherein peak concentrations of the transition metal dopant and the rare-earth metal dopant or the alkaline metal dopant in the second HK dielectric layer is at the interface between the second IL layer and the second HK dielectric layer; and
a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer.
2 . The semiconductor device of claim 1 , wherein the first dipole layer comprises rare-earth metal-based dipoles or alkaline metal-based dipoles.
3 . The semiconductor device of claim 1 , wherein the first dipole layer comprises n-type dipoles.
4 . The semiconductor device of claim 1 , wherein the second dipole layer comprises transition metal-based dipoles and rare-earth metal-based dipoles or alkaline metal-based dipoles.
5 . The semiconductor device of claim 1 , wherein the second dipole layer comprises n-type dipoles and p-type dipoles.
6 . The semiconductor device of claim 1 , wherein a concentration of the rare-earth metal dopant in the first HK dielectric layer is substantially equal to a concentration of the rare-earth metal dopant in the second HK dielectric layer.
7 . The semiconductor device of claim 1 , wherein a concentration of the rare-earth metal dopant in the first HK dielectric layer is greater than a concentration of the transition metal dopant in the second HK dielectric layer.
8 . The semiconductor device of claim 1 , wherein a concentration of the rare-earth metal dopant in the second HK dielectric layer is greater than a concentration of the transition metal dopant in the second HK dielectric layer.
9 . The semiconductor device of claim 1 , wherein a peak concentration of the rare-earth metal dopant or the alkaline metal dopant in the first HK dielectric layer is at the interface between the first IL layer and the first HK dielectric layer.
10 . The semiconductor device of claim 1 , wherein the second dipole layer comprises zinc-based p-type dipoles and lanthanum-based n-type dipoles.
11 . A semiconductor device, comprising:
a substrate;
a fin structure disposed on the substrate;
first and second nanostructured channel regions disposed on the fin structure;
a first gate structure disposed on the first nanostructured channel region, the first gate structure comprising:
a first oxide layer disposed on the first nanostructured channel region;
a first dielectric layer disposed on the first oxide layer, wherein the first dielectric layer comprises transition metal dopants, and wherein a peak concentration of the transition metal dopants is at an interface between the first oxide layer and the first dielectric layer; and
a p-type dipole layer disposed between the first dielectric layer and the first nanostructured channel region; and
a second gate structure disposed on the second nanostructured channel region, the second gate structure comprising:
a second oxide layer disposed on the second nanostructured channel region;
a second dielectric layer disposed on the second oxide layer, wherein the second dielectric layer comprises the transition metal dopants and alkaline metal dopants, and wherein peak concentrations of the transition metal dopants and alkaline metal dopants are at an interface between the second oxide layer and the second dielectric layer; and
a dipole layer with n-type dipoles and p-type dipoles disposed between the second dielectric layer and the second nanostructured channel region.
12 . The semiconductor device of claim 11 , wherein a concentration of the transition metal dopants in the first dielectric layer is substantially equal to a concentration of the transition metal dopants in the second dielectric layer.
13 . The semiconductor device of claim 11 , wherein a concentration of the transition metal dopants in the first dielectric layer is greater than a concentration of the alkaline metal dopants in the second dielectric layer.
14 . The semiconductor device of claim 11 , wherein the dipole layer comprises zinc-based p-type dipoles and magnesium-based n-type dipoles.
15 . The semiconductor device of claim 11 , wherein a concentration of p- type dipoles in the p-type dipole layer is substantially equal to a concentration of the p-type dipoles in the dipole layer.
16 . The semiconductor device of claim 11 , wherein a concentration of the p-type dipoles in the dipole layer is greater than a concentration of the n-type dipoles in the dipole layer.
17 . A semiconductor device, comprising:
a substrate;
a gate oxide layer disposed on the substrate;
a gate dielectric layer comprising gallium dopants and zinc dopants disposed on the gate oxide layer, wherein peak concentrations of the gallium dopants and the zinc dopants are at an interface between the gate oxide layer and the gate dielectric layer:
a dipole layer with first and second p-type dipoles disposed between the gate oxide layer and the gate dielectric layer,
a work function metal layer disposed on the gate dielectric layer; and
a gate metal fill layer disposed on the work function metal layer.
18 . The semiconductor device of claim 17 , wherein a concentration of the first p-type dipoles is equal to a concentration of the second p-type dipoles.
19 . The semiconductor device of claim 17 , wherein a total peak concentration of the gallium dopants and the zinc dopants in the gate dielectric layer is about 70 atomic % to about 80 atomic %.
20 . The semiconductor device of claim 17 , wherein concentrations of the metal gallium dopants and the zinc dopants are equal to each other.