Low-cost and low-voltage anti-fuse array
A low-cost and low-voltage anti-fuse array includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistor of all anti-fuse memory cells includes an anti-fuse gate commonly used by other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit-lines, wherein the anti-fuse memory cells in the same row are connected to different bit-lines, and all anti-fuse memory cells are connected to the same selection-line and different word-lines. The present invention utilizes the configuration of common source contacts to achieve a stable source structure and reduce the overall layout area, and meanwhile minimizes the types of control voltage to reduce leakage current.
1. A low-cost and low-voltage anti-fuse array, comprising:
a plurality of parallel bit-lines, comprising adjacent first bit-line and second bit-line;
a plurality of parallel word-lines, perpendicular to the bit-lines and comprising a first word-line, a second word-line, a third word-line and a fourth word-line;
a plurality of parallel selection-lines, parallel to the word-lines and comprising a first selection-line; and
a plurality of sub-memory arrays, each of the sub-memory arrays comprising:
a first anti-fuse memory cell connected to the first word-line, the first selection-line and the first bit-line;
a second anti-fuse memory cell connected to the second word-line, the first selection-line and the second bit-line, wherein the first anti-fuse memory cell and the second anti-fuse memory cell are adjacent to each other along the horizontal direction;
a third anti-fuse memory cell connected to the third word-line, the first selection-line and the first bit-line, wherein the third anti-fuse memory cell and the first anti-fuse memory cell are adjacent to each other along the vertical direction; and
a fourth anti-fuse memory cell connected to the fourth word-line, the first selection-line and the second bit-line, wherein the fourth anti-fuse memory cell is located at an intersection of the horizontal direction of the third anti-fuse memory cell and the vertical direction of the second anti-fuse memory cell, and the first, second, third and fourth anti-fuse memory cell are located between the first bit-line and the second bit-line;
wherein each of the first, second, third and fourth anti-fuse memory cell has an anti-fuse transistor, and only one of corners of a first gate dielectric layer of the anti-fuse transistor overlaps an anti-fuse gate.
2. The low-cost and low-voltage anti-fuse array according to claim 1 , wherein each of four corners of the anti-fuse gate overlaps a corner of a different first gate dielectric layer.
3. The low-cost and low-voltage anti-fuse array according to claim 2 , wherein each of the four corners of the anti-fuse gate forms at least one protruding corner which is smaller than or equal to 90 degrees.
4. The low-cost and low-voltage anti-fuse array according to claim 3 , wherein each of the four corners of the anti-fuse gate forms an extending part which has two protruding corners.
5. The low-cost and low-voltage anti-fuse array according to claim 1 , wherein the first anti-fuse memory cell comprises the anti-fuse transistor and a selection transistor, and the anti-fuse transistor comprises:
the anti-fuse gate, arranged on a substrate and connected to the first bit-line;
the first gate dielectric layer, arranged between the anti-fuse gate and the substrate; and
a first ion-doped region, arranged in the substrate on one side of the first gate dielectric layer, and connected to the first selection-line;
wherein the selection transistor comprises:
a selection gate, arranged on the substrate and connected to the first word-line;
a second gate dielectric layer, arranged between the selection gate and the substrate; and
a second ion-doped region, arranged in the substrate on the one side of the second gate dielectric layer that is away from the first ion-doped region, wherein the second ion-doped region is connected to the first selection-line, and the second ion-doped region is doped with the same type of ion of the first ion-doped region.
6. The low-cost and low-voltage anti-fuse array according to any of claim 5 , wherein the substrate is a P-type semiconductor substrate, and the ion-doped regions are N-type doped regions.
7. The low-cost and low-voltage anti-fuse array according to any of claim 5 , wherein the substrate is an N-type semiconductor substrate, and the ion-doped regions are P-type doped regions.
8. The low-cost and low-voltage anti-fuse array according to any of claim 5 , further comprising a well area arranged inside the substrate and located beneath the first ion-doped regions, wherein the well area is doped with a different type of ion of the first ion-doped region.
9. The low-cost and low-voltage anti-fuse array according to claim 1 , wherein the second anti-fuse memory cell comprises the anti-fuse transistor and a selection transistor, and the anti-fuse transistor comprises:
the anti-fuse gate, arranged on a substrate and connected to the second bit-line;
the first gate dielectric layer, arranged between the anti-fuse gate and the substrate; and
a first ion-doped region, arranged in the substrate on one side of the first gate dielectric layer, and connected to the first selection-line;
wherein the selection transistor comprises:
a selection gate, arranged on the substrate and connected to the second word-line;
a second gate dielectric layer, arranged between the selection gate and the substrate; and
a second ion-doped region, arranged in the substrate on one side of the second gate dielectric layer that is away from the first ion-doped region, wherein the second ion-doped region is connected to the first selection-line, and the second ion-doped region is doped with the same type of ion of the first ion-doped region.
10. The low-cost and low-voltage anti-fuse array according to any of claim 9 , wherein the substrate is a P-type semiconductor substrate, and the ion-doped regions are N-type doped regions.
11. The low-cost and low-voltage anti-fuse array according to any of claim 9 , wherein the substrate is an N-type semiconductor substrate, and the ion-doped regions are P-type doped regions.
12. The low-cost and low-voltage anti-fuse array according to any of claim 9 , further comprising a well area arranged inside the substrate and located beneath the first ion-doped regions, wherein the well area is doped with a different type of ion of the first ion-doped region.
13. The low-cost and low-voltage anti-fuse array according to claim 1 , wherein the third anti-fuse memory cell comprises the anti-fuse transistor and a selection transistor, and the anti-fuse transistor comprises:
the anti-fuse gate, arranged on a substrate and connected to the first bit-line;
the first gate dielectric layer, arranged between the anti-fuse gate and the substrate; and
a first ion-doped region, arranged in the substrate on the one side of the first gate dielectric layer, wherein the first ion-doped region is connected to the first selection-line;
wherein the selection transistor comprises:
a selection gate, arranged on the substrate and connected to the third word-line;
a second gate dielectric layer, arranged between the selection gate and the substrate; and
a second ion-doped region, arranged in the substrate on the one side of the second gate dielectric layer that is away from the first ion-doped region, wherein the second ion-doped region is connected to the first selection-line, and the second ion-doped region is doped with the same type of ion of the first ion-doped region.
14. The low-cost and low-voltage anti-fuse array according to any of claim 13 , wherein the substrate is a P-type semiconductor substrate, and the ion-doped regions are N-type doped regions.
15. The low-cost and low-voltage anti-fuse array according to any of claim 13 , wherein the substrate is an N-type semiconductor substrate, and the ion-doped regions are P-type doped regions.
16. The low-cost and low-voltage anti-fuse array according to any of claim 13 , further comprising a well area arranged inside the substrate and located beneath the first ion-doped regions, wherein the well area is doped with a different type of ion of the first ion-doped region.
17. The low-cost and low-voltage anti-fuse array according to claim 1 , wherein the fourth anti-fuse memory cell comprises the anti-fuse transistor and a selection transistor, and the anti-fuse transistor comprises:
the anti-fuse gate, arranged on a substrate and connected to the second bit-line;
the first gate dielectric layer, arranged between the anti-fuse gate and the substrate; and
a first ion-doped region, arranged in the substrate on one side of the first gate dielectric layer, and connected to the first selection-line;
wherein the selection transistor comprises:
a selection gate, arranged on the substrate and connected to the fourth word-line;
a second gate dielectric layer, arranged between the selection gate and the substrate; and
a second ion-doped region, arranged in the substrate on one side of the second gate dielectric layer that is away from the first ion-doped region, wherein second ion-doped region is connected to the first selection-line, and the second ion-doped region is doped with the same type of ion of the first ion-doped region.
18. The low-cost and low-voltage anti-fuse array according to any of claim 17 , wherein the substrate is a P-type semiconductor substrate, and the ion-doped regions are N-type doped regions.
19. The low-cost and low-voltage anti-fuse array according to any of claim 17 , wherein the substrate is an N-type semiconductor substrate, and the ion-doped regions are P-type doped regions.
20. The low-cost and low-voltage anti-fuse array according to any of claim 17 , further comprising a well area arranged inside the substrate and located beneath the first ion-doped regions, wherein the well area is doped with a different type of ion of the first ion-doped region.