IP Library › Granted Patent US 11,508,664
Granted Patent B2
US 11,508,664 · App. 16/861,891 · Granted Nov 22, 2022

Interconnect structure including graphene-metal barrier and method of manufacturing the same

Inventors: Keunwook Shin (Yongin-si, KR); Kibum Kim (Seoul, KR); Hyunmi Kim (Seoul, KR); Hyeonjin Shin (Suwon-si, KR); Sanghun Lee (Seoul, KR)
Assignees: Samsung Electronics Co., Ltd.; Seoul National University R&DB Foundation
H01L23/5386H01L23/5329H01L23/53204H01L24/19H01L29/1606
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Quick Facts
Patent No.
US 11,508,664
App. No.
16/861,891
Granted
Nov 22, 2022
Kind
B2
Abstract

An interconnect structure may include a graphene-metal barrier on a substrate and a conductive layer on the graphene-metal barrier. The graphene-metal barrier may include a plurality of graphene layers and metal particles on grain boundaries of each graphene layer between the plurality of graphene layers. The metal particles may be formed at a ratio of 1 atom % to 10 atom % with respect to carbon of the plurality of graphene layers.

Claims (64)

1. An interconnect structure comprising:

a substrate;

a graphene-metal barrier on the substrate, the graphene-metal barrier including a plurality of graphene layers and metal particles on a grain boundary of each of the plurality of graphene layers and between the plurality of graphene layers; and

a conductive layer on the graphene-metal barrier,

wherein all of the plurality of graphene layers are substantiality parallel to the conductive layer.

2. The interconnect structure of claim 1 , wherein the substrate includes a semiconductor and an insulator.

3. The interconnect structure of claim 1 , wherein the plurality of graphene layers includes three to ten graphene layers.

4. The interconnect structure of claim 1 , wherein the metal particles include Ru, Al, Ti, Pt, Ta, Rh, Ir, or Co.

5. The interconnect structure of claim 4 , wherein the metal particles include Ti or Ta, and the metal particles are metal carbides bound with carbon of at least one of the plurality of graphene layers between grain boundaries.

6. The interconnect structure of claim 1 , further comprising:

other metal particles between the substrate and the plurality of graphene layers and between the plurality of graphene layers and the conductive layer.

7. The interconnect structure of claim 1 , wherein the metal particles are formed at a ratio of 1 atom % to 10 atom % with respect to carbon of the plurality of graphene layers.

8. A method of manufacturing an interconnect structure including a graphene-metal barrier, the method comprising:

forming the graphene-metal barrier on a substrate, the forming the graphene-metal barrier including supplying a hydrocarbon gas and a metal precursor to the substrate, the graphene-metal barrier including a plurality of graphene layers and metal particles on a grain boundary of each of the plurality of graphene layers and between the plurality of graphene layers; and

forming a conductive layer on the graphene-metal barrier,

wherein all of the plurality of graphene layers are substantially parallel to the conductive layer.

9. The method of claim 8 , wherein the metal precursor includes Ru, Al, Ti, Pt, Ta, Pt, Ta, Rh, Ir, or Co.

10. The method of claim 8 , wherein the forming the graphene-metal barrier includes simultaneously supplying the hydrocarbon gas and the metal precursor to the substrate.

11. The method of claim 8 , wherein the forming the graphene-metal barrier includes repeatedly performing operations of alternately supplying the hydrocarbon gas and the metal precursor to the substrate.

12. The method of claim 8 , wherein

the forming the graphene-metal barrier includes forming a first graphene layer including a plurality of graphene islands and forming metal particles on graphene grain boundaries of the first graphene layer, and

the forming the graphene-metal barrier further includes forming a second graphene layer including a plurality of graphene islands over the first graphene layer, wherein

the forming the first graphene layer and the forming the second graphene layer include supplying the hydrocarbon gas to the substrate,

the forming metal particles on graphene grain boundaries of the first graphene layer includes supplying the metal precursor to the substrate,

the metal particles on the graphene grain boundaries of the first graphene layer act as catalysts for growing the plurality of graphene islands of the second graphene layer,

the plurality of graphene layers include the first graphene layer and the second graphene layer, and the metal particles are formed between graphene grains in the first graphene layer and the second graphene layer.

13. The method of claim 12 , wherein

the metal precursor includes Ti and Ta, and

the metal particles include TiC and TaC metal carbide combined with carbon of a corresponding graphene layer among the plurality of graphene layers.

14. The method of claim 8 , wherein the plurality of graphene layers include three to ten graphene layers.

15. The method of claim 8 , wherein in the graphene-metal barrier, the metal particles are formed at a ratio of 1 atom % to 10 atom % with respect to carbon of the plurality of graphene layers.

16. The method of claim 8 , wherein the forming the graphene-metal barrier includes:

forming a structure including the plurality of graphene layers and the metal particles between the plurality of graphene layers; and

moving some of the metal particles between the plurality of graphene layers to a grain boundary of the plurality of graphene layer by annealing the structure before forming the conductive layer, wherein some of the metal particles cover the grain boundary of plurality of graphene layers.

17. The method of claim 8 , wherein the forming the graphene-metal barrier includes forming the metal particles between the substrate and the plurality of graphene layers and between a corresponding one of the plurality of graphene layers and the conductive layer.

18. The method of claim 16 , wherein the graphene-metal barrier is formed using a chemical vapor deposition (CVD) process.

19. The method of claim 17 , wherein the graphene-metal barrier is formed using a plasma-enhanced chemical vapor deposition (PECVD) process.

20. An interconnect structure comprising:

a substrate;

a conductive layer on the substrate; and

a graphene-metal barrier between the conductive layer and the substrate, the graphene-metal barrier including a plurality of graphene layers arranged on each other and metal particles, each of the plurality of graphene layers including grains separated by grain boundaries, and

a first portion of the metal particles being on or in corresponding grain boundaries among the grain boundaries of at least two of the plurality of graphene layers,

wherein all of the plurality of graphene layers are substantially parallel to the conductive layer.

21. The interconnect structure of claim 20 , wherein a second portion of the metal particles are between adjacent graphene layers among the plurality of graphene layers.

22. The interconnect structure of claim 20 , wherein a third portion of the metal particles are between the substrate and one of the plurality of graphene layers that is closest to the substrate.

23. An electronic device comprising:

an understructure;

a barrier on the understructure; and

a contact structure on the barrier,

wherein the barrier is the graphene-metal barrier described in claim 20 .

24. The electronic device of claim 23 ,

further comprising an insulating layer on the understructure and including a hole exposing a portion of the understructure, wherein

the barrier covers the portion exposed by the hole of the understructure and inner side surfaces of the hole, and

the hole, the inner side surfaces of which are covered by the barrier is filled with the contact structure.

25. The electronic device of claim 24 , wherein the understructure is a device portion having a semiconductor region, and the semiconductor region is exposed through the hole.

26. The electronic device of claim 24 , wherein

the understructure includes:

a substrate; and

a material layer on the substrate,

wherein the material layer is exposed through the hole.

27. The electronic device of claim 24 , further comprising an

electrode layer on the insulating layer,

wherein the electrode layer covers the hole and contacts the contact structure and the barrier.

28. The electronic device of claim 24 , wherein the barrier extends on the insulating layer around the hole, and the contact structure extends on an extended portion of the barrier.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2020
From: SHIN, KEUNWOOK; SHIN, HYEONJIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 052561/0717 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2020
From: KIM, KIBUM; KIM, HYUNMI; LEE, SANGHUN
To: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
Reel/Frame 052561/0738 →
Priority Claims (2)
KR 10-2019-0050992 · Apr 30, 2019 · national
KR 10-2020-0051832 · Apr 28, 2020 · national
Continuity (1)
Related Publication 20200350252A1 · Nov 5, 2020
Cited By (1)
US 12,199,165