Structure and formation method of hybrid semiconductor device

1. A method for forming a hybrid semiconductor device structure, comprising:

providing a substrate having a first region and a second region;

epitaxially forming alternating stacked films over the substrate;

forming a trench in the alternating stacked films over the first region;

after forming the trench, patterning the alternating stacked films over the second region to obtain an alternating stacked fin;

filling the trench over the first region with a material different from that of the substrate;

patterning the material over the first region to obtain a fin;

depositing a first dummy gate dielectric layer over the fin;

forming a dummy gate extending across the fin and the alternating stacked fin;

removing the dummy gate over the fin to expose the first dummy gate dielectric layer;

annealing the fin so as to transform the first dummy gate dielectric layer to a second dummy gate dielectric layer, wherein the second dummy gate dielectric layer is thicker than the first dummy gate dielectric layer; and

removing the second dummy gate dielectric layer.

2. The method of claim 1 , wherein the patterning of the alternating stacked films over the second region and the patterning of the material over the first region are performed concurrently.

3. The method of claim 1 , further comprising:

covering the fin over the first region with a mask;

releasing at least one nanostructure from the alternating stacked fin; and

removing the mask covering the fin after the at least one nanostructure is released.

4. The method of claim 1 , wherein the trench is a tapered trench tapering toward the substrate.

5. The method of claim 1 , further comprising:

depositing a first dummy gate dielectric layer over the fin; and

annealing the fin so as to transform the first gate dielectric layer to a second dummy gate dielectric layer before forming the dummy gate over the fin, wherein the second dummy gate dielectric layer is thicker than the first dummy gate dielectric layer.

6. The method of claim 1 , wherein topmost surfaces of the material and the alternating stacked films are substantially level with each other.

7. A method for forming a hybrid semiconductor device structure, comprising:

providing a substrate having a first region and a second region;

alternately and sequentially depositing a first material layer and a second material layer to form alternating stacked films over the first region and the second region of the substrate;

partially removing the alternating stacked films to form a trench over the first region;

after the trench is formed, patterning the alternating stacked films over the second region to form an alternating stacked fin;

filling the trench with a semiconductor material;

patterning the semiconductor material to form a semiconductor fin;

forming a dummy gate over the semiconductor fin and the alternating stacked fin;

forming a dielectric layer to surround the dummy gate;

removing the dummy gate after the dielectric layer is formed; and

releasing at least one nanostructure from the alternating stacked fin after the dummy gate is removed.

8. The method of claim 7 , further comprising:

depositing a first dummy gate dielectric layer over the semiconductor fin; and

annealing the semiconductor fin so as to transform the first dummy gate dielectric layer to a second dummy gate dielectric layer before the forming of the dummy gate, wherein the second dummy gate dielectric layer is thicker than the first dummy gate dielectric layer.

9. The method of claim 7 , further comprising:

depositing a first dummy gate dielectric layer over the semiconductor fin;

removing the dummy gate to expose the first dummy gate dielectric layer;

annealing the semiconductor fin so as to transform the first dummy gate dielectric layer to a second dummy gate dielectric layer, wherein the second dummy gate dielectric layer is thicker than the first dummy gate dielectric layer; and

removing the second dummy gate dielectric layer.

10. The method of claim 7 , wherein the at least one nanostructure comprises a nanowire.

11. The method of claim 7 , wherein the semiconductor material completely fills the trench.

12. A method for forming a semiconductor device structure, comprising:

forming a stacked film over a substrate, wherein the stacked film has a plurality of first material layers and a plurality of second material layers laid out alternatively;

replacing a portion of the stacked film with a semiconductor material;

patterning the stacked film to form an alternating stacked fin;

patterning the semiconductor material to form a semiconductor fin;

forming a dummy gate extending across the alternating stacked fin and the semiconductor fin;

forming a dielectric layer to surround the dummy gate, the alternating stacked fin, and the semiconductor fin;

removing the dummy gate to form a trench exposing the alternating stacked fin and the semiconductor fin; and

releasing a plurality of nanostructures from the alternating stacked fin after the dummy gate is removed.

13. The method of claim 12 , wherein the alternating stacked fin and the semiconductor fin are formed concurrently.

14. The method of claim 12 , wherein the substrate is made of a material other than that of the semiconductor fin.

15. The method of claim 12 , wherein the alternating stacked fin and the semiconductor fin are formed to have respective topmost surfaces substantially level with each other.

16. The method of claim 12 , wherein the alternating stacked fin and the semiconductor fin are formed to have different widths.

17. The method of claim 16 , wherein the alternating stacked fin is formed to be wider than the semiconductor fin.

18. The method of claim 12 , wherein the metal gate stack comprises a gate dielectric layer, and a portion of the gate dielectric layer is between the substrate and a bottommost surface of the nanostructures.

19. The method of claim 12 , wherein the dummy gate continuously extends across the alternating stacked fin and the semiconductor fin.

20. The method of claim 12 , further comprising:

depositing a first dummy gate dielectric layer over the semiconductor fin;

removing the dummy gate over the semiconductor fin to expose the first dummy gate dielectric layer;

annealing the semiconductor fin so as to transform the first dummy gate dielectric layer to a second dummy gate dielectric layer, wherein the second dummy gate dielectric layer is thicker than the first dummy gate dielectric layer; and

removing the second dummy gate dielectric layer.