Method for fabricating semiconductor device with programmable feature

1. A method for fabricating a semiconductor device, comprising:

forming a semiconductor fin on a buried insulating layer;

forming a dummy gate structure on the semiconductor fin;

forming a top insulating layer over the semiconductor fin and covering the dummy gate structure;

removing the dummy gate structure and concurrently forming a first trench in the top insulating layer;

performing an etch process in the first trench to form a tapered pit separating the semiconductor fin;

forming a first insulating layer to completely fill the first trench and the tapered pit; and

replacing the semiconductor fin with first conductive blocks.

2. The method for fabricating the semiconductor device of claim 1 , wherein the step of replacing the semiconductor fin into the first conductive blocks comprises:

forming contact openings in the top insulating layer;

removing the semiconductor fin through the contact openings and concurrently forming first voids on two sides of the first insulating layer; and

forming the first conductive blocks to completely fill the first voids.

3. The method for fabricating the semiconductor device of claim 2 , wherein the etch process comprises using an alkaline aqueous based etchant in the first trench to form the tapered pit.

4. The method for fabricating the semiconductor device of claim 3 , wherein sidewalls of the tapered pit have <111> crystal orientation.

5. The method for fabricating the semiconductor device of claim 3 , further comprising a step of forming impurity regions on the semiconductor fin before the step of forming the top insulating layer over the semiconductor fin and covering the dummy gate structure.

6. The method for fabricating the semiconductor device of claim 1 , wherein the first insulating layer comprises a peak portion and an upper portion on the peak portion, and the method further comprises:

forming first spacers on two sides of the upper portion.

7. The method for fabricating the semiconductor device of claim 1 , wherein a width of the peak portion is gradually decreased toward a direction opposite to the upper portion, and the first conductive blocks are spaced apart by the peak portion.

8. The method for fabricating the semiconductor device of claim 1 , wherein a bottom surface of the top insulating layer is at a vertical level above a vertical level of bottom surfaces of the first spacers.

9. The method for fabricating the semiconductor device of claim 8 , wherein a top surface of the first insulating layer and top surfaces of the first conductive blocks are substantially coplanar.

10. The method for fabricating the semiconductor device of claim 9 , wherein a bottommost point of the peak portion is at a same vertical level as bottom surfaces of the first conductive blocks.

11. The method for fabricating the semiconductor device of claim 9 , wherein a bottommost point of the peak portion is at a vertical level lower than a vertical level of bottom surfaces of the first conductive blocks.

12. The method for fabricating the semiconductor device of claim 10 , wherein an angle between the two sides of the peak portion is between about 60 degree and about 80 degree.

13. The method for fabricating the semiconductor device of claim 1 , further comprising: forming a bottom layer below the buried insulating layer.