Adjustable NAND write performance
Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.
1. A memory device for adjustable write performance, the memory device comprising:
an interface to receive, from a controller of the memory device, a write request for a target block that is opened as a multi-level cell (MLC) encoded block; and
processing circuitry to:
determine that the write request is accelerated over a standard write request received from the controller; and
write data to the target block using a single-level cell (SLC) encoding instead of MLC encoding based on the determination that the write request is accelerated.
2. The memory device of claim 1 , wherein the processing circuitry is configured to fill a first element of the target block encoded with the MLC encoding prior to a write of the data for the write request to a second element of the target block that is encoded with the SLC encoding.
3. The memory device of claim 2 , wherein the first element and the second element are pages in the target block.
4. The memory device of claim 1 , wherein the SLC encoding has charge distributions based on charge distributions for a type of MLC encoding for the target block.
5. The memory device of claim 1 , wherein, to determine that the write request is accelerated over a standard write request, the processing circuitry is configured to determine that the memory device is in a high-speed mode of operation when the write request is received.
6. The memory device of claim 5 , wherein the processing circuitry is configured to put the memory device into the high-speed mode of operation in response to an explicit request from a host.
7. The memory device of claim 5 , wherein the processing circuitry is configured to put the memory device into the high-speed mode of operation in response to a workload detected by the processing circuitry.
8. The memory device of claim 1 , wherein, to determine that the write request is accelerated over a standard write request, the processing circuitry is configured to:
determine that the memory device is not in a high-speed mode of operation; and
extract a field from the write request that indicates the command is accelerated.
9. A method for adjustable write performance in a memory device, the method comprising:
receiving, from a controller of the memory device, a write request for a target block that is opened as a multi-level cell (MLC) encoded block;
determining that the write request is accelerated over a standard write request received from the controller; and
writing data to the target block using a single-level cell (SLC) encoding instead of MLC encoding based on the determination that the write request is accelerated.
10. The method of claim 9 comprising filling a first element of the target block encoded with the MLC encoding prior to writing the data for the write request to a second element of the target block that is encoded with the SLC encoding.
11. The method of claim 10 , wherein the first element and the second element are pages in the target block.
12. The method of claim 9 , wherein the SLC encoding has charge distributions based on charge distributions for a type of MLC encoding for the target block.
13. The method of claim 9 , wherein determining that the write request is accelerated over a standard write request includes determining that the memory device is in a high-speed mode of operation when the write request is received.
14. The method of claim 13 , comprising putting the memory device into the high-speed mode of operation in response to an explicit request from a host.
15. The method of claim 13 , wherein the memory device is put into the high-speed mode of operation in response to a workload detected by the processing circuitry.
16. The method of claim 9 , wherein determining that the write request is accelerated over a standard write request includes:
determining that the memory device is not in a high-speed mode of operation; and
extracting a field from the write request that indicates the command is accelerated.
17. A non-transitory machine readable medium including instructions for adjustable write performance in a memory device, the instructions, when executed by processing circuitry of the memory device, cause the processing circuitry to perform operations comprising:
receiving, from a controller of the memory device, a write request for a target block that is opened as a multi-level cell (MLC) encoded block;
determining that the write request is accelerated over a standard write request received from the controller; and
writing data to the target block using a single-level cell (SLC) encoding instead of MLC encoding based on the determination that the write request is accelerated.
18. The non-transitory machine readable medium of claim 17 , wherein the operations comprise filling a first element of the target block encoded with the MLC encoding prior to writing the data for the write request to a second element of the target block that is encoded with the SLC encoding.
19. The non-transitory machine readable medium of claim 18 , wherein the first element and the second element are pages in the target block.
20. The non-transitory machine readable medium of claim 17 , wherein the SLC encoding has charge distributions based on charge distributions for a type of MLC encoding for the target block.
21. The non-transitory machine readable medium of claim 17 , wherein determining that the write request is accelerated over a standard write request includes determining that the memory device is in a high-speed mode of operation when the write request is received.
22. The non-transitory machine readable medium of claim 21 , wherein the operations comprise putting the memory device into the high-speed mode of operation in response to an explicit request from a host.
23. The non-transitory machine readable medium of claim 21 , wherein the memory device is put into the high-speed mode of operation in response to a workload detected by the processing circuitry.
24. The non-transitory machine readable medium of claim 17 , wherein determining that the write request is accelerated over a standard write request includes:
determining that the memory device is not in a high-speed mode of operation; and
extracting a field from the write request that indicates the command is accelerated.