TSV structure and method forming same
A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.
1. A method comprising:
forming a plurality of dielectric layers over a semiconductor substrate;
etching the plurality of dielectric layers and the semiconductor substrate to form an opening;
depositing a first liner extending into the opening, wherein a first bottom end of the first liner is higher than a second bottom end of the opening;
depositing a second liner over the first liner, wherein the second liner extends into the opening;
filling a conductive material into the opening to form a through-via; and
forming conductive features on opposite sides of the semiconductor substrate, wherein the conductive features are electrically interconnected through the through-via.
2. The method of claim 1 , wherein the depositing the first liner is performed using a non-conformal deposition method.
3. The method of claim 2 , wherein the depositing the second liner is performed using a conformal deposition method.
4. The method of claim 1 , wherein the first bottom end of the first liner is level with a top surface of the semiconductor substrate.
5. The method of claim 1 , wherein the first bottom end of the first liner is higher than a top surface of the semiconductor substrate.
6. The method of claim 1 , wherein the first bottom end of the first liner is lower than a top surface of the semiconductor substrate.
7. The method of claim 1 , wherein the depositing the first liner comprises depositing a conductive liner, and the depositing the second liner comprises depositing a dielectric liner.
8. The method of claim 1 , wherein the depositing the first liner comprises depositing silicon nitride, and the depositing the second liner comprises depositing silicon oxide.
9. The method of claim 1 , wherein the depositing the first liner comprises depositing silicon carbide, and the depositing the second liner comprises depositing silicon oxide.
10. A method comprising:
forming a plurality of dielectric layers over a semiconductor substrate;
etching the plurality of dielectric layers and the semiconductor substrate to form an opening;
forming a first liner extending into the opening;
forming a second liner extending into the opening and on the first liner, wherein the second liner has a lower density than the first liner;
filling the opening with a conductive material;
forming a first conductive feature and a second conductive feature, wherein the first conductive feature and the second conductive feature are on opposite sides of a combined region comprising the plurality of dielectric layers and the semiconductor substrate; and
forming a through-via from the conductive material, wherein the through-via electrically interconnects the first conductive feature and the second conductive feature.
11. The method of claim 10 , wherein the second liner is in physical contact with the through-via, and the first liner is in physical contact with a top portion of the second liner, and is spaced apart from a lower portion of the second liner.
12. The method of claim 10 , wherein a bottom end of the first liner is level with a top surface of the semiconductor substrate.
13. The method of claim 10 , wherein a bottom end of the first liner is higher than a top surface of the semiconductor substrate.
14. The method of claim 10 , wherein a bottom end of the second liner is lower than a top surface of the semiconductor substrate.
15. The method of claim 10 , wherein at a time after both of the first liner and the second liner are formed, the first liner has a bottom end higher than a bottom surface of the semiconductor substrate.
16. The method of claim 10 , wherein the forming the first liner comprises depositing a first sub layer and depositing a second sub layer on the first sub layer, and wherein bottom ends of the first sub layer and the second sub layer are at different levels.
17. A method comprising:
forming a die comprising:
forming a plurality of low-k dielectric layers over a semiconductor substrate;
forming a through-via penetrating through the semiconductor substrate and the plurality of low-k dielectric layers;
forming a first liner encircling the through-via, wherein the first liner extends to both a top end and a bottom end of the through-via;
forming a second liner encircling the first liner, wherein the second liner is shorter than the through-via;
forming a first electrical connector over the semiconductor substrate and at a top surface of the die; and
forming a second electrical connector underlying the semiconductor substrate and at a bottom surface of the die, wherein the first electrical connector and the second electrical connector are electrically interconnected through the through-via.
18. The method of claim 17 , wherein the second liner is denser than the first liner.
19. The method of claim 17 , wherein the second liner is thinner than the first liner.
20. The method of claim 17 , wherein the first liner penetrates through the semiconductor substrate, and wherein the second liner higher than the semiconductor substrate.