IP Library Granted Patent US 11,545,464
Granted Patent B2
US 11,545,464 · App. 16/235,859 · Granted Jan 3, 2023

Diode for use in testing semiconductor packages

Inventors: Yi Xu (Folsom, CA); Hyoung Il Kim (Folsom, CA); Florence Pon (Folsom, CA)
Assignee: Intel Corporation
H01L25/0657H01L22/12H01L22/34H01L2225/0651H01L2225/06506H01L2225/06562H01L2225/06586H01L2225/06596
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Quick Facts
Patent No.
US 11,545,464
App. No.
16/235,859
Granted
Jan 3, 2023
Kind
B2
Abstract

Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad.

Claims (32)

1. A semiconductor package, comprising:

a die stack comprising one or more dies;

a molding compound encapsulating the die stack;

a substrate over the molding compound;

a test pad on a surface of the substrate;

a contact pad on the surface of the substrate and electrically coupled to the die stack; and

a diode coupling the test pad to the contact pad, the diode comprising a P-N junction.

2. The semiconductor package of claim 1 , wherein the test pad is coupled to a P-side of the P-N junction of the diode and the contact pad is coupled to an N-side of the P-N junction of the diode.

3. The semiconductor package of claim 1 , wherein the test pad is coupled to an N-side of the P-N junction of the diode and the contact pad is coupled to a P-side of the P-N junction of the diode.

4. The semiconductor package of claim 1 , wherein the diode is embedded in the substrate.

5. The semiconductor package of claim 1 , wherein the diode is encapsulated by the molding compound.

6. The semiconductor package of claim 5 , wherein the diode is in contact with the die stack.

7. The semiconductor package of claim 5 , wherein the diode is adjacent to the die stack.

8. The semiconductor package of claim 1 , wherein the diode is a signal diode or a rectifier diode.

9. The semiconductor package of claim 1 , wherein the contact pad is a high speed input/output interface.

10. A packaged system, comprising:

a semiconductor package, comprising:

a die stack comprising a plurality of dies;

a molding compound encapsulating the die stack;

a redistribution layer over the molding compound;

a plurality of test pads on a surface of the redistribution layer;

a plurality of contact pads on the surface of the redistribution layer and electrically coupled to the die stack by a wire bond embedded in the molding compound; and

a plurality of diodes, each diode comprising a P-N junction, wherein a first terminal of each diode is electrically coupled to one of the contact pads by a conductive trace, and wherein a second terminal of each diode is electrically coupled to one of the test pads by a conductive trace; and

a printed circuit board, wherein the semiconductor package is electrically coupled to the printed circuit board by interconnects contacting the contact pads.

11. The packaged system of claim 10 , wherein the test pads are coupled to a P-side terminal of the P-N junction of the diode and the contact pads are coupled to an N-side terminal of the P-N junction of the diode.

12. The packaged system of claim 10 , wherein the test pads are coupled to an N-side of the P-N junction of the diode and the contact pads are coupled to a P-side of the P-N junction of the diode.

13. The packaged system of claim 10 , wherein the diodes are embedded in the redistribution layer.

14. The packaged system of claim 10 , wherein at least one of the diodes is a signal diode or a rectifier diode.

15. The packaged system of claim 10 , wherein at least one of the contact pads is a high speed input/output interface.

16. The packaged system of claim 10 , wherein the diodes are encapsulated by the molding compound.

17. The packaged system of claim 16 , wherein the diodes are in contact with the die stack.

18. The packaged system of claim 16 , wherein the diodes are adjacent to the die stack.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072850/0834 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2019
From: XU, YI; KIM, HYOUNG IL; PON, FLORENCE
To: INTEL CORPORATION
Reel/Frame 048402/0600 →
Continuity (1)
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