Three-dimensional memory device and method

1. A device comprising:

a first dielectric layer having a first sidewall;

a second dielectric layer having a second sidewall;

a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall;

a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and

a semiconductor layer extending along the memory layer.

2. The device of claim 1 , wherein the word line has a connecting surface extending between the outer sidewall and the inner sidewall, the connecting surface and the inner sidewall forming a right angle.

3. The device of claim 1 , wherein the word line has a connecting surface extending between the outer sidewall and the inner sidewall, the connecting surface and the inner sidewall forming an obtuse angle.

4. The device of claim 1 , wherein the word line has a connecting surface extending between the outer sidewall and the inner sidewall, the connecting surface and the inner sidewall forming a sharp corner.

5. The device of claim 1 , wherein the word line has a connecting surface extending between the outer sidewall and the inner sidewall, the connecting surface and the inner sidewall forming a rounded corner.

6. The device of claim 1 , wherein the inner sidewall is recessed from the outer sidewall by a depth in a range of 10 nm to 50 nm.

7. The device of claim 1 further comprising:

a bit line contacting a sidewall of the semiconductor layer and a sidewall of the memory layer;

a source line contacting the sidewall of the semiconductor layer and the sidewall of the memory layer; and

an isolation region between the source line and the bit line, the isolation region contacting the sidewall of the semiconductor layer and the sidewall of the memory layer.

8. The device of claim 1 further comprising:

a bit line contacting a sidewall of the semiconductor layer;

a source line contacting the sidewall of the semiconductor layer; and

an isolation region between the source line and the bit line, the semiconductor layer separating a sidewall of the memory layer from each of the source line, the bit line, and the isolation region.

9. The device of claim 1 further comprising:

a bit line contacting a sidewall of the semiconductor layer;

a source line contacting the sidewall of the semiconductor layer; and

an isolation region between the source line and the bit line, the semiconductor layer and the isolation region separating a sidewall of the memory layer from each of the source line and the bit line.

10. A device comprising:

a word line comprising a main portion, a first projecting portion, and a second projecting portion, the first projecting portion and the second projecting portion each extending away from opposite sides of the main portion;

a memory layer extending along the word line, a portion of the memory layer disposed between the first projecting portion and the second projecting portion of the word line;

a semiconductor layer extending along the memory layer, a portion of the semiconductor layer disposed between the first projecting portion and the second projecting portion of the word line; and

a conductive line extending along the semiconductor layer.

11. The device of claim 10 , wherein a portion of the conductive line is disposed between the first projecting portion and the second projecting portion of the word line.

12. The device of claim 10 , wherein a portion of the semiconductor layer is disposed between the conductive line and the main portion of the word line.

13. The device of claim 10 , wherein a thickness of the first projecting portion and the second projecting portion is from 5% to 30% of a thickness of the main portion.

14. A method comprising:

forming a first conductive material between layers of a dielectric material;

recessing a sidewall of the first conductive material from sidewalls of the dielectric material to form a sidewall recess;

depositing a second conductive material in the sidewall recess;

patterning the second conductive material to define a word line comprising the first conductive material and the second conductive material;

forming a memory layer in the sidewall recess, the memory layer contacting the word line; and

forming a semiconductor layer contacting the memory layer.

15. The method of claim 14 , wherein the first conductive material and the second conductive material are a same conductive material.

16. The method of claim 14 , wherein the first conductive material and the second conductive material are different conductive materials.

17. The method of claim 14 , wherein patterning the second conductive material comprises:

etching the second conductive material to remove portions of the second conductive material on the sidewalls of the dielectric material.

18. The method of claim 17 , wherein etching the second conductive material comprises:

performing an anisotropic dry etch using a fluorine-based gas mixed with oxygen gas.

19. The method of claim 18 , wherein the anisotropic dry etch removes the second conductive material from 2 to 5 times faster than the dielectric material.

20. The method of claim 14 , wherein after depositing the second conductive material, the sidewall recess have a depth in a range of 10 nm to 50 nm.