Semiconductor structure

1. A semiconductor structure comprising:

a molding;

a device disposed in the molding; and

a redistribution layer (RDL) over the device and the molding,

wherein the RDL comprises a first portion directly over a surface of the molding, a second portion directly over a surface of the device, a bottom surface of the first portion is in contact with the surface of the molding, a bottom surface of the second portion is in contact with the surface of the device, the bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other, and a thickness of the first portion is greater than a thickness of the second portion.

2. The semiconductor structure of claim 1 , wherein the device comprises at least a die pad, and a surface of the die pad is substantially aligned with the surface of the device.

3. The semiconductor structure of claim 2 , wherein the RDL further comprises a conductive interconnect structure in contact with the die pad.

4. The semiconductor structure of claim 1 , further comprising a bond pad disposed over and electrically connected to the RDL.

5. The semiconductor structure of claim 1 , wherein the thickness of the first portion of the RDL is substantially greater than the thickness of the second portion of the RDL about 5 μm.

6. The semiconductor structure of claim 1 , wherein the device includes an unpackaged device or a packaged device.

7. The semiconductor structure of claim 1 , further comprising a pair of metallic shields disposed at two sides of the device in the molding.

8. The semiconductor structure of claim 7 , further comprising a metallic layer coupled to the pair of metallic shields.

9. The semiconductor structure of claim 8 , wherein the metallic layer covers a surface of the molding opposite to the RDL.

10. A system in package (SiP) comprising:

a molding;

a device disposed in the molding;

a pair of metallic shields disposed within the molding and at two sides of the device; and

a redistribution layer (RDL) disposed over the device and the molding,

wherein the RDL comprises a first portion directly over the molding, a second portion directly over the device, a bottom surface of the first portion is in contact with a surface of the molding, a bottom surface of the second portion is in contact with a surface of the device, the bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other, and a thickness of the first portion is greater than a thickness of the second portion.

11. The system in package of claim 10 , wherein the RDL comprises a first conductive interconnect structure disposed in the second portion, and the device is electrically connected to the first conductive interconnect structure of the RDL.

12. The system in package of claim 11 , further comprising at least a die pad disposed in the device and electrically connected to the first conductive interconnect structure.

13. The system in package of claim 11 , wherein the RDL comprise a second conductive interconnect structure disposed in the first portion, and the metallic shield is electrically connected to the second conductive interconnect structure of the RDL.

14. The system in package of claim 13 , wherein a thickness of the second conductive interconnect structure is greater than a thickness of the first conductive interconnect structures.

15. The system in package of claim 10 , further comprising a bond pad disposed over and electrically connected to the RDL.

16. A semiconductor structure, comprising:

a metallic layer;

a molding disposed over the metallic layer;

a device surrounded by the molding;

a pair of metallic shields disposed within the molding and at two sides of the device,

wherein the pair of metallic shields is in contact with the metallic layer; and

a redistribution layer (RDL) disposed over the molding, the device and the pair of metallic shields,

wherein the RDL comprises a first portion directly over the molding, a second portion directly over the plurality of the devices, a bottom surface of the first portion is in contact with a surface of the molding, a bottom surface of the second portion is in contact with a surface of the device, the bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other, and a thickness of the first portion is greater than a thickness of the second portion.

17. The semiconductor structure of claim 16 , wherein the RDL comprises:

at least a first conductive interconnect structure disposed in the second portion; and

at least a second conductive interconnect structure disposed in the first portion and electrically isolated from the plurality of first conductive interconnect structures,

wherein the first conductive interconnect structure is electrically connected to the device, and the second conductive interconnect structure is electrically connected to at least one of the metallic shields.

18. The semiconductor structure of claim 17 , wherein a thickness of the second conductive interconnect structures is greater than a thickness of the first conductive interconnect structures.

19. The semiconductor structure of claim 17 , further comprising at least a die pad disposed in the device and electrically connected to the first conductive interconnect structure.

20. The semiconductor structure of claim 16 , further comprising a bond pad disposed over and electrically connected to the RDL.