Semiconductor devices and methods of manufacturing thereof
A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.
1. A semiconductor device, comprising:
a channel structure, extending along a first lateral direction, that is disposed over a substrate;
a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure;
an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure;
an air gap disposed between the gate structure and the epitaxial structure along the first lateral direction, wherein the air gap comprises a first portion that extends along a vertical direction and has a bottom end disposed above a top surface of the channel structure;
a first gate spacer comprising a first portion disposed between the first portion of the air gap and the gate structure; and
a second gate spacer disposed over the air gap;
wherein the first gate spacer comprises a first layer and a second layer, the first layer disposed between the second layer and the gate structure along the first lateral direction, and wherein one of the first layer or second layer of the first gate spacer extends only along the vertical direction.
2. The semiconductor device of claim 1 , wherein the air gap further comprises a second portion, extending along the first lateral direction, that is disposed above the top surface of the channel structure.
3. The semiconductor device of claim 2 , wherein the second portion of the air gap is connected to the bottom end of the first portion of the air gap, thereby forming an L-shaped profile.
4. The semiconductor device of claim 2 , wherein the second portion is disposed between the epitaxial structure and the gate structure along the first lateral direction.
5. The semiconductor device of claim 1 , wherein the second gate spacer has a bottom end disposed above the top surface of the channel structure.
6. The semiconductor device of claim 1 , wherein the first gate spacer comprises a second portion, extending along the first lateral direction, that is disposed above the top surface of the channel structure.
7. The semiconductor device of claim 6 , wherein the second portion of the first gate spacer is connected to the first portion of the first gate spacer, thereby forming an L-shaped profile.
8. The semiconductor device of claim 1 , wherein the first layer has a portion that extends only along the vertical direction and is disposed above the top surface of the channel structure, and the second layer has a plurality of portions that collectively form an L-shaped profile above the top surface of the channel structure.
9. The semiconductor device of claim 1 , wherein the first layer has a plurality of portions that collectively form an L-shaped profile above the top surface of the channel structure, and the second layer has a portion that extends only along the first lateral direction.
10. The semiconductor device of claim 1 , wherein the channel structure comprises a plurality of nanostructures separated from one another along the vertical direction.
11. A semiconductor device, comprising:
a gate structure extending along a first lateral direction;
a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction;
an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure; and
a first gate spacer and a second gate spacer disposed between the source/drain structure and the gate structure along the second lateral direction, wherein the air gap is sandwiched between the first and second gate spacers;
wherein the first gate spacer comprises a first layer and a second layer, the first layer disposed between the second layer and the gate structure along the second lateral direction, and wherein one of the first layer or second layer of the first gate spacer extends only along a vertical direction.
12. The semiconductor device of claim 11 , wherein the air gap comprises:
a first portion extending along the vertical direction; and
a second portion extending along the second lateral direction.
13. The semiconductor device of claim 12 , wherein the first and second portions of the air gap collectively form an L-shaped profile.
14. The semiconductor device of claim 11 , further comprising a plurality of nanostructures separated from one another along the vertical direction, each of the plurality of nanostructures extending along the second lateral direction.
15. The semiconductor device of claim 14 , wherein the gate structure wraps around each of the plurality of nanostructures, wherein the source/drain structure is coupled to one end of each of the plurality of nanostructures, and wherein the air gap is disposed above a topmost one of the plurality of nanostructures.
16. A method for fabricating semiconductor devices, comprising:
forming a channel structure over a substrate, wherein the channel structure extends along a first lateral direction;
forming a gate structure extending along a second lateral direction and straddling a portion of the channel structure;
forming a first gate spacer straddling another portion of the channel structure;
forming a sacrificial gate spacer over the first gate spacer, wherein the sacrificial gate spacer has a bottom surface vertically above a top surface of the channel structure;
forming a second gate spacer over the sacrificial gate spacer; and
removing the sacrificial gate spacer to form an air gap;
wherein the first gate spacer comprises a first layer and a second layer, the first layer disposed between the second layer and the gate structure along the second lateral direction, and wherein one of the first layer or second layer of the first gate spacer extends only along a vertical direction.
17. The method of claim 16 , prior to the step of removing the sacrificial gate spacer, further comprising:
growing an epitaxial structure coupled to the channel structure, wherein the first gate spacer is disposed between the epitaxial structure and the gate structure along the first lateral direction; and
overlaying the epitaxial structure with a dielectric material.
18. The method of claim 16 , wherein the first layer has a portion that extends only along the vertical direction and is disposed above the top surface of the channel structure, and the second layer has a plurality of portions that collectively form an L-shaped profile above the top surface of the channel structure.
19. The method of claim 16 , wherein the first layer has a plurality of portions that collectively form an L-shaped profile above the top surface of the channel structure, and the second layer has a portion that extends only along the first lateral direction.
20. The method of claim 16 , wherein the channel structure comprises a plurality of nanostructures separated from one another along the vertical direction.