Semiconductor devices and methods of manufacturing thereof
A method for fabricating semiconductor devices includes forming a channel structure over a substrate and along a first lateral direction; forming a gate structure extending along a second lateral direction and straddling a portion of the channel structure; forming a gate spacer along a side of the gate structure, the gate spacer having a lateral portion and a vertical portion; growing an epitaxial structure over the channel structure; and forming an air gap within the gate spacer. The air gap is entirely above the epitaxial structure and vertically separated from the epitaxial structure by the lateral portion of the gate spacer.
1. A method for fabricating a semiconductor device, comprising:
forming a channel structure over a substrate and along a lateral direction;
forming a gate structure along a second lateral direction, wherein the gate structure straddles a first portion of the channel structure;
forming a gate spacer along a side of the gate structure, wherein the gate spacer has a lateral portion and a vertical portion;
forming a sacrificial gate spacer over the gate spacer, wherein the sacrificial gate spacer covers both the lateral portion and the vertical portion;
removing a second portion of the channel structure, wherein the second portion is adjacent to the first portion along the lateral direction, and wherein removing the second portion of the channel structure removes portions of the gate spacer and the sacrificial gate spacer;
after removing the second portion of the channel structure, growing an epitaxial structure over a sidewall of a remaining portion of the channel structure; and
removing a remaining portion of the sacrificial gate spacer to form an air gap that is entirely disposed between the gate spacer and the epitaxial structure along the lateral direction.
2. The method of claim 1 , wherein the air gap is laterally separated from the gate structure by the vertical portion of the gate spacer.
3. The method of claim 1 , wherein the air gap has an L-shaped profile.
4. The method of claim 1 , wherein the gate spacer is formed entirely above the epitaxial structure by a dimension in a range from 0.3 nm to 20 nm.
5. The method of claim 4 , wherein the range of the dimension is from 5 nm to 15 nm.
6. The method of claim 1 , wherein:
the lateral portion is a first lateral portion and the vertical portion is a first lateral portion, and
the air gap has a second vertical portion interposed between the first vertical portion and a sidewall of the epitaxial structure, and a second lateral portion entirely disposed adjacent to a top surface of the epitaxial structure.
7. The method of claim 1 , prior to removing the remaining portion of the sacrificial gate spacer, further comprising overlaying the epitaxial structure with a dielectric material.
8. The method of claim 1 , wherein:
the gate spacer is a first gate spacer, the lateral portion is a first lateral portion, and the vertical portion is a first vertical portion,
the method further comprises forming a second gate spacer after forming the sacrificial gate spacer and prior to removing the portions of the semiconductor fin, the gate spacer, and the sacrificial gate spacer, and
the second gate spacer has a second lateral portion and a second vertical portion over the first lateral portion and the first vertical portion, respectively.
9. The method of claim 8 , wherein removing the portions of the semiconductor fin, the gate spacer, and the sacrificial gate spacer removes an entirety of the second lateral portion.
10. The method of claim 7 , wherein the air gap exposes a portion of the dielectric material.
11. A method for fabricating semiconductor devices, comprising:
forming a channel structure over a substrate and along a lateral direction;
forming a dummy gate structure extending along a second lateral direction and straddling a first portion of the channel structure;
forming a gate spacer along a side of the dummy gate structure, wherein the gate spacer has a first bottom portion extending away from the dummy gate structure over a second portion of the channel structure along the lateral direction;
forming a sacrificial gate spacer over an entirety of the gate spacer;
recessing the second portion of the channel structure and portions of the sacrificial gate spacer and the gate spacer disposed over the second portion;
growing an epitaxial structure over a sidewall of the recessed channel structure; and
forming an air gap to replace remaining portions of the sacrificial gate spacer, wherein an entirety of the air gap is vertically above the epitaxial structure and between the dummy gate structure along the lateral direction.
12. The method of claim 11 , wherein the entirety of the air gap is vertically separated from the epitaxial structure by the bottom portion of the gate spacer.
13. The method of claim 11 , further comprising:
forming an interlayer dielectric (ILD) layer over the epitaxial structure prior to forming the air gap; and
replacing the dummy gate structure with a metal gate structure after forming the ILD layer.
14. The method of claim 11 , wherein the gate spacer is formed entirely above the epitaxial structure by a dimension in a range from 0.3 nm to 20 nm.
15. The method of claim 11 , wherein the air gap has an L-shaped profile.
16. The method of claim 13 , wherein:
the air gap has a second bottom portion extending over the first bottom portion, and
the ILD layer extends over the second bottom portion of the air gap along a vertical direction.
17. The method of claim 11 , wherein:
the gate spacer is a first gate spacer, and
the method further comprises forming a second gate spacer over the entirety of the sacrificial gate spacer prior to recessing the portions of the sacrificial gate spacer and the gate spacer.
18. A method for fabricating semiconductor devices, comprising:
forming a channel structure over a substrate and along a lateral direction;
forming a first gate spacer straddling a first portion of the channel structure, wherein the first gate spacer has a bottom portion that fills a space surrounding a second portion of the channel structure, and wherein the second portion is adjacent to the first portion along the lateral direction;
forming a sacrificial gate spacer over the first gate spacer, wherein sidewalls of the second portion of the channel structure are free of any portions of the sacrificial gate spacer;
forming a second gate spacer over the sacrificial gate spacer;
removing the second portion of the channel structure, the bottom portion of the gate spacer, and a bottom portion of the sacrificial gate spacer to expose a sidewall of the first portion of the channel structure;
forming an epitaxial structure over the exposed sidewall of the channel structure, wherein a top surface of the epitaxial structure is below a remaining portion of the gate spacer; and
after forming the epitaxial structure, removing the sacrificial gate spacer to form an air gap, wherein the air gap is entirely above the channel structure.
19. The method of claim 18 , prior to removing the sacrificial gate spacer, further comprising overlaying the epitaxial structure with a dielectric material, wherein the dielectric material extends over a bottom portion of the air gap.
20. The method of claim 18 , wherein air gap is vertically above the epitaxial structure by a dimension in a range from 0.3 nm to 20 nm.