IP Library › Granted Patent US 11,563,119
Granted Patent B2
US 11,563,119 · App. 16/650,834 · Granted Jan 24, 2023

Etchstop regions in fins of semiconductor devices

Inventors: Cheng-Ying Huang (Hillsboro, OR); Willy Rachmady (Beaverton, OR); Gilbert Dewey (Hillsboro, OR); Erica J. Thompson (Beaverton, OR); Aaron D. Lilak (Beaverton, OR); Jack T. Kavalieros (Portland, OR)
Assignee: Intel Corporation
H01L29/785H01L29/165H01L29/66803H01L29/7848
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Quick Facts
Patent No.
US 11,563,119
App. No.
16/650,834
Granted
Jan 24, 2023
Kind
B2
Abstract

Disclosed are etchstop regions in fins of semiconductor devices, and related methods. A semiconductor device includes a buried region, a fin on the buried region, and a gate formed at least partially around the fin. At least a portion of the fin that borders the buried region includes an etchstop material. The etchstop material includes a doped semiconductor material that has a slower etch rate than that of an intrinsic form of the semiconductor material. A method of manufacturing a semiconductor device includes forming a gate on a fin, implanting part of the fin with dopants configured to decrease an etch rate of the part of the fin, removing at least part of the fin, and forming an epitaxial semiconductor material on a remaining proximal portion of the fin.

Claims (24)

1. A semiconductor device, comprising:

a buried region comprising an oxide material;

a fin on the buried region, at least a portion of the fin that borders the buried region comprising an etchstop material, the etchstop material comprising a doped semiconductor material, wherein the fin further comprises a doped epitaxial semiconductor material on the etchstop material; and

a gate formed at least partially around a portion of the fin, the gate comprising electrically conductive material, wherein the doped epitaxial semiconductor material is in contact with the portion of the fin beneath the gate.

2. The semiconductor device of claim 1 , wherein the doped semiconductor material of the etchstop material comprises a p-type doped semiconductor material.

3. The semiconductor device of claim 2 , wherein the p-type doped semiconductor material comprises boron doped silicon.

4. The semiconductor device of claim 1 , wherein the doped semiconductor material comprises a carbon doped silicon.

5. The semiconductor device of claim 1 , wherein the doped semiconductor material comprises at least one n-type doped semiconductor material selected from the list consisting of phosphorus, arsenic, and antimony.

6. The semiconductor device of claim 1 , wherein the portion of the fin around which the gate was formed comprises an intrinsic form of the semiconductor material.

7. The semiconductor device of claim 1 , wherein the fin further comprises silicon and germanium epitaxially formed on the etchstop material, the silicon and germanium doped with a p-type dopant selected from the group consisting of boron, aluminum, gallium, and indium.

8. The semiconductor device of claim 1 , wherein the doped epitaxial semiconductor material comprises silicon epitaxially formed on the etchstop material, the silicon doped with at least one n-type dopant selected from the group consisting of phosphorus, arsenic, antimony, and tellurium.

9. The semiconductor device of claim 1 , wherein the buried region comprises a buried oxide (BOX) of a silicon on insulator (SOI) substrate.

10. A method of manufacturing a semiconductor device, the method comprising:

forming a gate on a fin comprising semiconductor material;

implanting part of a proximate portion of the fin that is proximate to a buried region comprising electrically insulating material with dopants configured to decrease an etch rate of the semiconductor material;

removing at least part of a distal portion of the fin that is remote from the buried region;

forming an epitaxial semiconductor material on a remaining proximal portion of the fin; and

forming a gate at least partially around a portion of the fin, the gate comprising electrically conductive material, wherein the epitaxial semiconductor material is in contact with the portion of the fin beneath the gate.

11. The method of claim 10 , wherein implanting part of a proximate portion of the fin with dopants comprises implanting the proximate portion of the fin with boron.

12. The method of claim 10 , wherein implanting part of a proximate portion of the fin with dopants comprises implanting the proximate portion of the fin with carbon.

13. The method of claim 10 , further comprising doping the distal portion of the fin with an amorphization implant prior to removing the distal portion of the fin.

14. The method of claim 13 , wherein doping the distal portion of the fin with an amorphization implant comprises:

doping the distal portion of the fin with silicon for an n-type device; or

doping the distal portion of the fin with silicon and germanium for a p-type device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072792/0266 →
Continuity (1)
Related Publication 20200279941A1 · Sep 3, 2020