IP Library › Granted Patent US 11,569,169
Granted Patent B2
US 11,569,169 · App. 16/485,552 · Granted Jan 31, 2023

Semiconductor device comprising electronic components electrically joined to each other via metal nanoparticle sintered layer and method of manufacturing the same

Inventor: Tsuyoshi Tanigaki (Chiyoda-ku, JP)
Assignee: MITSUBISHI ELECTRIC CORPORATION
H01L23/53252H01L21/477H01L21/76841H01L23/528H01L23/53238H01L23/53266
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Quick Facts
Patent No.
US 11,569,169
App. No.
16/485,552
Granted
Jan 31, 2023
Kind
B2
Abstract

Provided is a semiconductor device including electronic components electrically joined to each other via a metal nanoparticle sintered layer, wherein the metal nanoparticle sintered layer has formed therein a metal diffusion region in which a metal constituting a metallization layer formed on a surface of one of the electronic components is diffused, and in which the metal is present in an amount of 10 mass % or more and less than 100 mass % according to TEM-EDS analysis, and wherein the metal diffusion region has a thickness smaller than a thickness of the metallization layer.

Claims (8)

1. A semiconductor device, comprising electronic components electrically joined to each other via a metal nanoparticle sintered layer,

wherein the metal nanoparticle sintered layer has formed therein a metal diffusion region in which a metal constituting a metallization layer formed on a surface of one of the electronic components is diffused, and in which the metal is present in an amount of 10 mass % or more and less than 100 mass % according to TEM-EDS analysis, and

wherein the metal diffusion region has a thickness smaller than a thickness of the metallization layer,

wherein the metal nanoparticle sintered layer is only composed of a layer formed by applying a paste containing organic material-coated Ag nanoparticles to form a Ag nanoparticle layer, and sintering the Ag nanoparticle layer, and

wherein the metallization layer includes Au, Cu, Ni, or Ti as a main component.

2. The semiconductor device according to claim 1 , wherein the metal diffusion region has a thickness of 1 nm or more and less than 100 nm.

3. The semiconductor device according to claim 1 , wherein a surface of the metallization layer includes a pattern of irregularities each having a size of 1 or less.

4. The semiconductor device according to claim 1 , wherein the metallization layer consists of Au, Cu, Ni, or Ti.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2019
From: TANIGAKI, TSUYOSHI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 050037/0060 →
Priority Claims (1)
JP JP2017-059464 · Mar 24, 2017 · national
Continuity (1)
Related Publication 20200006243A1 · Jan 2, 2020