IP Library Granted Patent US 11,569,362
Granted Patent B2
US 11,569,362 · App. 16/927,953 · Granted Jan 31, 2023

Semiconductor device and a method for fabricating the same

Inventors: Chia-Ming Hsu (Hualien County, TW); Pei-Yu Chou (Hsinchu County, TW); Chih-Pin Tsao (Zhubei, TW); Kuang-Yuan Hsu (Taichung, TW); Jyh-Huei Chen (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L29/45H01L21/32053H01L21/76802H01L21/76832H01L21/76834H01L21/76849H01L21/76867H01L21/76877H01L21/76889H01L21/76897H01L21/823418H01L23/485H01L23/53209H01L23/53238H01L23/53266H01L27/0886H01L29/41791H01L29/665H01L29/66795H01L21/0214H01L21/0217H01L21/02167H01L21/28518H01L21/76805H01L21/76843H01L21/76855H01L29/7848
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Quick Facts
Patent No.
US 11,569,362
App. No.
16/927,953
Granted
Jan 31, 2023
Kind
B2
Abstract

A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

Claims (50)

1. A semiconductor device including a field effect transistor, comprising:

a source/drain region;

a source/drain silicide layer formed on the source/drain region;

a first contact disposed in the interlayer dielectric layer over the source/drain silicide layer; and

a second contact disposed over the first contact, wherein:

the first contact includes a first metal layer,

an upper surface of the first metal layer is partially covered by a silicide layer,

the silicide layer includes a same metal element as the first metal layer,

a bottom of the second contact is in direct contact with the first metal layer and is located above a bottom surface of the silicide layer.

2. The semiconductor device of claim 1 , wherein:

the first contact further includes an adhesive layer, and

the adhesive layer is disposed between the first metal layer and the source/drain silicide layer.

3. The semiconductor device of claim 1 , further comprising a dielectric layer, in which the first contact is embedded,

wherein the silicide layer protrudes above an upper surface of dielectric layer.

4. The semiconductor device of claim 1 , wherein the silicide layer is made of Co silicide and the first metal layer is made of Co.

5. The semiconductor device of claim 1 , further comprising:

a dielectric layer, in which the first contact is embedded; and

an insulating layer in contact with the silicide layer and the dielectric layer,

wherein the insulating layer is made of a different material than the dielectric layer.

6. The semiconductor device of claim 1 , wherein the bottom of the second contact is in contact with the upper surface of the first metal layer.

7. A semiconductor device including a field effect transistor, comprising:

a first interlayer dielectric layer;

a first contact including a first metal layer, embedded in the first interlayer dielectric layer and disposed over an underlying conductive layer;

an adhesive layer disposed between the first contact and the underlying conductive layer;

a first silicide layer partially covering an upper surface of the first metal layer;

an insulating layer disposed over the first interlayer dielectric layer;

a second interlayer dielectric layer disposed over the insulating layer; and

a second contact embedded in the second interlayer dielectric layer and in contact with at least one of the silicide layer and the first contact, wherein:

the silicide layer is made of Co silicide and the first metal layer is made of Co, and

a bottom of the second contact is in contact with the first metal layer.

8. The semiconductor device of claim 7 , wherein the bottom of the second contact is in contact with the upper surface of the first metal layer.

9. The semiconductor device of claim 8 , wherein the insulating layer is in contact with a part of the upper surface of the first metal layer.

10. The semiconductor device of claim 9 , wherein the silicide layer is in contact with the insulating layer.

11. The semiconductor device of claim 9 , wherein the silicide layer is in contact with the adhesive layer.

12. The semiconductor device of claim 7 , wherein the bottom of the second contact is located above a bottom surface of the silicide layer.

13. The semiconductor device of claim 7 , wherein the insulating layer is made of a different material than the first and second interlayer dielectric layers.

14. The semiconductor device of claim 13 , wherein the insulating layer includes at least one selected from the group consisting of SiN, SiC, SiCN and SiON.

15. A semiconductor device including a field effect transistor, comprising:

a first contact disposed over a conductive portion formed over a substrate and embedded in an interlayer dielectric layer;

an adhesive layer disposed between the interlayer dielectric layer and the first contact; and

a second contact disposed over the first contact, wherein:

the first contact includes a first metal layer,

an upper surface of the first metal layer is partially covered by a silicide layer,

the silicide layer includes a same metal element as the first metal layer, and

the bottom of the second contact is in direct contact with and the first metal layer and is located above a bottom surface of the silicide layer.

16. The semiconductor device of claim 15 , wherein a bottom of the second contact is in contact with the first metal layer.

17. The semiconductor device of claim 16 , wherein the bottom of the second contact is located above an upper surface of the silicide layer.

18. The semiconductor device of claim 15 , wherein the adhesive layer includes a TiN layer formed on a Ti layer.

19. The semiconductor device of claim 15 , wherein the adhesive layer is in contact with the silicide layer.

20. The semiconductor device of claim 15 , wherein the silicide layer is made of Co silicide and the first metal layer is made of Co.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: HSU, CHIA-MING; CHOU, PEI-YU; TSAO, CHIH-PIN; HSU, KUANG-YUAN; CHEN, JYH-HUEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 053196/0230 →
Continuity (4)
Division 16049589 · Jul 30, 2018
Division 15378574 · Dec 17, 2016
Provisional Application 62289148 · Jan 29, 2016
Related Publication 20200350416A1 · Nov 5, 2020