Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices
A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other.
1. A method of manufacturing a 3D semiconductor device, the method comprising:
forming a first target structure, the first target structure including at least one upper gate connected to a first active layer, at least one bottom gate connected to a second active layer, at least one common gate connected to the first active layer and the second active layer, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate;
simultaneously removing material in at least two of a plurality of material removal areas in the first target structure, the plurality of material removal areas including a first area that extends through the at least one upper gate to a top of the dielectric separation layer, a second area that provides a diffusion break, and a third area that provides a lateral cut that is perpendicular to the at least one common gate, wherein the at least two of the plurality of material removal areas includes at least two of the first area, the second area, and the third area; and
forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other.
2. The method of manufacturing according to claim 1 , wherein the removing of the material includes simultaneously removing the material in the at least two of the plurality of material removal areas via an etching process.
3. The method of manufacturing according to claim 2 , wherein the removing of the material includes simultaneously removing all of the plurality of material removal areas via the etching process.
4. The method of manufacturing according to claim 1 ,
wherein the at least two of the plurality of material removal areas includes the second area,
wherein the first target structure further includes at least one dummy gate, and
wherein the diffusion break is a single diffusion break that cuts entirely through the at least one dummy gate.
5. The method of manufacturing according to claim 1 ,
wherein the at least two of the plurality of material removal areas includes the second area and the third area, and
wherein the diffusion break extends perpendicularly to the lateral cut.
6. The method of manufacturing according to claim 1 ,
wherein the at least two of the plurality of material removal areas includes the third area,
wherein the at least one common gate is spaced from and parallel to both the at least one upper gate and the at least one bottom gate, and
wherein the lateral cut extends downward through the at least one common gate, the at least one upper gate, and the at least one bottom gate to form terminations of each of the respective gates.
7. The method of manufacturing according to claim 1 , wherein the forming the first target structure further includes:
forming the at least one bottom gate via metallization;
depositing a dielectric material on top of the at least one bottom gate to form the dielectric separation layer; and
forming the at least one upper gate via metallization.
8. The method of manufacturing according to claim 1 ,
wherein the at least two of the plurality of material removal areas includes the first area,
wherein the first area provides a vertical cut,
wherein the at least one upper gate includes a first upper gate and a second upper gate,
wherein the vertical cut includes a first vertical cut and a second vertical cut, and
wherein the first vertical cut is formed in the first upper gate and the second vertical cut is formed in the second upper gate.
9. The method of manufacturing according to claim 8 , wherein the first vertical cut and second vertical cut are formed on opposite sides of the first active layer.
10. The method of manufacturing according to claim 1 , wherein the first contact and second contact extend from a top of the first target structure to the at least one upper gate and at least one bottom gate, respectively.
11. The method of manufacturing according to claim 1 ,
wherein the at least one upper gate is part of an N-type field-effect-transistor (FET) and the at least one bottom gate is part of a P-type FET; or
wherein the at least one upper gate is part of an P-type FET and the at least one bottom gate is part of an N-type FET.
12. The method of manufacturing according to claim 1 , wherein the method further includes forming a third contact establishing a third electrical connection to the at least one common gate.
13. The method of manufacturing according to claim 12 , wherein the forming of the third contact, the forming of the first contact, and the forming of the second contact occur simultaneously.