Method of forming semiconductor device including deep vias
A method (of manufacturing a semiconductor device) includes: forming via structures in a first via layer over a transistor layer; forming a first via structure of a first deep via arrangement in the first via layer; forming conductive segments in a first metallization layer over the first via layer; forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value and which is included in the first deep via arrangement; and forming via structures in a second via layer over the first metallization layer, including forming a first via structure of the first deep via arrangement in the second via layer.
1. A method of manufacturing a semiconductor device, the method comprising:
forming via structures in a first via layer over a transistor layer, the forming via structures in the first via layer including:
forming a first via structure in the first via layer, the first via structure being included in a first deep via arrangement;
forming conductive segments in a first metallization layer over the first via layer, the forming theconductive segments in the first metallization layer including:
forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; and
forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value, the M_1st interconnection segment being included in the first deep via arrangement; and
forming via structures in a second via layer over the first metallization layer, the forming the via structures in the second via layer including:
forming a first via structure in the second via layer, the first via structure being included in the first deep via arrangement.
2. The method of claim 1 , wherein the forming the M_1st interconnection segment includes:
aligning the M_1st interconnection segment to substantially overlap the first via structure in the first via layer.
3. The method of claim 1 , wherein the forming the first via structure in the second via layer, includes:
aligning the first via structure in the second via layer to substantially overlap the M_1st interconnection segment in the first metallization layer.
4. The method of claim 1 , the method further comprising:
forming conductive segments in a second metallization layer over the second via layer, the forming the conductive segments in the second metallization layer including:
forming an M_2nd routing segment; and
aligning the M_2nd routing segment to substantially overlap the first via structure in the second via layer.
5. The method of claim 4 , the method further comprising:
forming via structures in a third via layer over the first metallization layer, the forming via structures in the third via layer including:
forming a first via structure in the third via layer, the first via structure being included in a second deep via arrangement;
forming conductive segments in a third metallization layer over the third via layer, the forming the conductive segments in the third metallization layer including:
forming M_3rd routing segments at least a majority of which, relative to the first direction, have corresponding long axes with lengths which at least equal if not exceed a second permissible minimum value for routing segments in the third metallization layer; and
forming an M_3rd interconnection segment having a long axis which is less than the second permissible minimum value, the M_3rd interconnection segment being included in the second deep via arrangement;
forming via structures in a fourth via layer over the transistor layer, the forming the via structures in the fourth via layer including:
forming a first via structure in the fourth via layer, the first via structure being included in the second deep via arrangement.
6. The method of claim 5 , wherein the forming the M_3rd interconnection segment includes:
aligning the M_3rd interconnection segment to substantially overlap the first via structure in the third via layer.
7. The method of claim 5 , wherein the forming the first via structure in the fourth via layer further includes:
aligning the first via structure of the fourth via layer to substantially overlap the M_3rd interconnection segment in the first metallization layer.
8. The method of claim 5 , the method further comprising:
forming conductive segments in a fourth metallization layer over the fourth via layer, the forming the conductive segments in the fourth metallization layer including:
forming an M_4th routing segment; and
aligning the M_4th routing segment to substantially overlap the first via structure in the fourth via layer.
9. The method of claim 1 , wherein the forming the first via layer further includes: forming a first shallow via structure in the first via layer.
10. The method of claim 9 , wherein the forming the conductive segments in the first metallization layer further includes:
aligning the M_1st routing segment to substantially overlap the first shallow via structure in the first via layer.
11. A method of manufacturing a semiconductor device, the method comprising:
forming via structures in a first via layer over a transistor layer, the forming the first via layer including:
forming a first via structure in the first via layer, the first via structure being included in a first deep via arrangement;
forming conductive segments in a first metallization layer over the first via layer, the forming conductive segments in the first metallization layer including:
forming an M_1st interconnection segment having a long axis which is less than a first permissible minimum value for M_1st routing segments in the first metallization layer, the M_1st interconnection segment being included in the first deep via arrangement; and
forming via structures in a second via layer over the transistor layer, the forming the via structures in the second via layer including:
forming a first via structure in the second via layer, the first via structure being included in the first deep via arrangement.
12. The method of claim 11 , wherein the forming the M_1st interconnection segment includes:
aligning the M_1st interconnection segment to substantially overlap the first via structure in the first via layer.
13. The method of claim 11 , wherein the forming the first via structure in the second via layer, includes:
aligning the first via structure of the second via layer to substantially overlap the M_1st interconnection segment in the first metallization layer.
14. The method of claim 11 , the method further comprising:
forming conductive segments in a second metallization layer over the second via layer, the forming the segments in the second metallization layer including:
forming an M_2nd routing segments; and
aligning one M_2nd routing segment to substantially overlap the first via structure in the second via layer.
15. The method of claim 14 , the method further comprising:
forming via structures in a third via layer over the first metallization layer, the forming via structures in the third via layer including:
forming a first via structure in the third via layer, the first via structure being included in a second deep via arrangement;
forming conductive segments in a third metallization layer over the third via layer, the forming the conductive segments in the third metallization layer including:
forming an M_3rd interconnection segment having a long axis which is less than a second permissible minimum value for M_3rd routing segments in the third metallization layer, the M_3rd interconnection segment being included in the second deep via arrangement; and
forming via structures in a fourth via layer over the transistor layer, the forming the via structures in the fourth via layer including:
forming a first via structure in the fourth via layer, the first via structure being included in the second deep via arrangement.
16. The method of claim 15 , wherein the forming the M_3rd interconnection segment includes:
aligning the M_3rd interconnection segment to substantially overlap the first via structure in the third via layer.
17. The method of claim 15 , wherein the forming the first via structure in the fourth via layer further includes:
aligning the first via structure of the fourth via layer to substantially overlap the M_3rd interconnection segment in the first metallization layer.
18. The method of claim 15 , the method further comprising:
forming conductive segments in a fourth metallization layer over the fourth via layer, the forming the conductive segments in the fourth metallization layer including:
forming an M_4th routing segment.
19. The method of claim 18 , wherein the forming the conductive segments in the fourth metallization layer over the fourth via layer including:
aligning the M_4th routing segment to substantially overlap the first deep via arrangement.
20. A method of manufacturing a semiconductor device, the method comprising:
forming via structures in a via layer V(i) over a transistor layer, where i is a non-negative integer, the forming the via structures in the via layer V(i) including:
forming a first via structure in the via layer V(i), the first via structure being included in a first deep via arrangement;
forming conductive segments in a metallization layer M(i) over the via layer V(i), where i is a non-negative integer, the forming the conductive segments in the metallization layer M(i) including:
forming first routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the metallization layer M(i); and
forming a first interconnection segment having a long axis which is less than the first permissible minimum value, the first interconnection segment being included in the first deep via arrangement; and
forming via structures in a via layer V(i+1) over the transistor layer, the forming the via structures in a via layer V(i+1) including:
forming a first via structure in the via layer V(i+1), the via structure V(i) being included in the first deep via arrangement.