Verifying method for ECC circuit of SRAM

1. A verifying method for an error checking and correcting (ECC) circuit of a static random-access memory (SRAM), comprising:

inputting original data into an error-correcting-and-coding procedure to output first data;

obtaining second data according to an error-injecting mask;

performing a bit operation on the first data and the second data to obtain third data;

writing the third data into a test target area in the SRAM to be fourth data;

reading the fourth data from the test target area;

inputting the fourth data into an error-correcting-and-decoding procedure to output fifth data and an error message; and

obtaining a verification result according to the fifth data, the original data, the error message, and the second data.

2. The verifying method for an ECC circuit of an SRAM according to claim 1 , wherein the step of inputting the original data into the error-correcting-and-coding procedure to output the first data comprises: adjusting the original data having an original bit length to the first data having an operation bit length.

3. The verifying method for an ECC circuit of an SRAM according to claim 2 , wherein the step of obtaining the second data according to the error-injecting mask comprises:

setting a bit length of the error-injecting mask according to the operation bit length;

selecting at least one error-injecting bit from the error-injecting mask; and

writing error-injecting data into the at least one error-injecting bit to obtain the second data.

4. The verifying method for an ECC circuit of an SRAM according to claim 3 , wherein the step of obtaining the second data according to the error-injecting mask further comprises:

repeatedly selecting other bits from the error-injecting mask to be the at least one error-injecting bit, until all of bits of the error-injecting mask have been selected.

5. The verifying method for an ECC circuit of an SRAM according to claim 4 , wherein the step of repeatedly selecting the other bits from the error-injecting mask to be the at least one error-injecting bit comprises:

obtaining the other bits of the error-injecting mask by repeatedly shifting a first incremental distance from the selected at least one error-injecting bit.

6. The verifying method for an ECC circuit of an SRAM according to claim 4 , wherein the step of repeatedly selecting the other bits from the error-injecting mask to be the at least one error-injecting bit comprises:

randomly selecting the other bits in the error-injecting mask that have not been selected to obtain at least one new error-injecting bit.

7. The verifying method for an ECC circuit of an SRAM according to claim 3 wherein the step of writing the third data into the test target area in the SRAM to be the fourth data comprises:

selecting a memory address from the SRAM; and

using the memory address as a start address of the test target area, wherein a bit length of the test target area is identical to a bit length of the third data.

8. The verifying method for an ECC circuit of an SRAM according to claim 7 , wherein the step of writing the third data into the test target area in the SRAM to be the fourth data further comprises:

selecting an address section from the test target area, wherein a bit length of the address section is identical to the bit length of the third data; and

writing the third data into the address section to be the fourth data.

9. The verifying method for an ECC circuit of an SRAM according to claim 3 wherein the step of writing the third data into the test target area in the SRAM to be the fourth data further comprises:

obtaining a start address and an end address of the SRAM; and

defining a space from the start address to the end address to be the test target area, wherein a bit length of the test target area is greater than or equal to a bit length of the third data.

10. The verifying method for an ECC circuit of an SRAM according to claim 9 , wherein the step of writing the third data into the test target area in the SRAM to be the fourth data further comprises:

selecting an address section from the test target area, wherein a bit length of the address section is identical to the bit length of the third data; and

writing the third data into the address section as the fourth data.

11. The verifying method for an ECC circuit of an SRAM according to claim 8 , wherein the step of writing the third data into the test target area in the SRAM to be the fourth data further comprises:

repeatedly selecting another address section at other positions from the test target area, until all of the address section of the test target area have been selected.

12. The verifying method for an ECC circuit of an SRAM according to claim 11 , wherein the step of repeatedly selecting the another address section at the other positions from the test target area comprises:

obtaining the another address section starting from an address section shifted from the address section by a second incremental distance.

13. The verifying method for an ECC circuit of an SRAM according to claim 11 , wherein the step of repeatedly selecting the another address section at the other positions from the test target area comprises:

randomly selecting other addresses in the test target area that have not been selected to obtain the another address section.

14. The verifying method for an ECC circuit of an SRAM according to claim 1 , wherein the bit operation is selected from an OR operation or an exclusive-OR operation.