Verification process for bit spreading error resistant memory system
View Patent ↗Techniques are provided for design verification of a bit spreading memory. A methodology implementing the techniques according to an embodiment includes using a bit spreading geometry file to convert a logical address of the memory to a physical address. The geometry file defines a scheme by which bits of a data word stored at the logical address are spread over multiple RAMs. The method also includes writing data bits of a test data word to the physical address, causing a design simulator to simulate a read from the logical address, and comparing the result to the test data word for verification. The method further includes causing the design simulator to simulate a write of the test data word to the logical address, reading data bits from the physical address, arranging the bits into a retrieved data word, and comparing the test data word to the retrieved data word for verification.
1. A computer program product including one or more non-transitory machine-readable mediums encoded with instructions that when executed by one or more processors cause a process to be carried out for verification of a design of a memory, the process comprising:
using a bit spreading geometry file to convert a logical address of the memory to a physical address, wherein the bit spreading geometry file defines a bit spreading scheme by which data bits of a data word stored at the logical address are stored in a spread fashion over a plurality of random access memories (RAM s) of the memory;
writing data bits of a test data word to the physical address;
causing a design simulator to simulate a read from the logical address; and
comparing a result of the simulated read to the test data word to verify the design of the memory;
wherein the bit spreading geometry file is configured to specify a logical base address of the memory, a size of the memory, and a description of the each of the plurality of RAMs.
2. The computer program product of claim 1 , wherein the process further comprises:
causing the design simulator to simulate a write of the test data word to the logical address;
reading data bits from the physical address;
arranging the data bits to form a retrieved data word; and
comparing the test data word to the retrieved data word to further verify the design of the memory.
3. The computer program product of claim 1 , wherein the description of the each of the plurality of RAMs includes a number of blocks of the RAM, a number of bits of each of the blocks of the RAM, and an identifying label of the RAM.
4. The computer program product of claim 1 , wherein the process iterates over additional logical addresses.
5. The computer program product of claim 1 , wherein the design of the memory is represented as a register transfer level description configured for execution by the design simulator.
6. The computer program product of claim 1 , wherein the process is implemented in Verilog and conforms to a Universal Verification Methodology.
7. A method for verification of a design of a memory, the method comprising:
using, by a processor-based system, a bit spreading geometry file to convert a logical address of the memory to a physical address, wherein the bit spreading geometry file defines a bit spreading scheme by which data bits of a data word stored at the logical address are stored in a spread fashion over a plurality of random access memories (RAMs) of the memory;
writing, by the processor-based system, data bits of a test data word to the physical address;
causing, by the processor-based system, a design simulator to simulate a read from the logical address; and
comparing, by the processor-based system, a result of the simulated read to the test data word to verify the design of the memory;
wherein the bit spreading geometry file is configured to specify a logical base address of the memory, a size of the memory, and a description of the each of the plurality of RAMs.
8. The method of claim 7 , further comprising:
causing the design simulator to simulate a write of the test data word to the logical address;
reading data bits from the physical address;
arranging the data bits to form a retrieved data word; and
comparing the test data word to the retrieved data word to further verify the design of the memory.
9. The method of claim 7 , wherein the description of the each of the plurality of RAMs includes a number of blocks of the RAM, a number of bits of each of the blocks of the RAM, and an identifying label of the RAM.
10. The method of claim 7 , wherein the method iterates over additional logical addresses.
11. The method of claim 7 , wherein the design of the memory is represented as a register transfer level description configured for execution by the design simulator.
12. The method of claim 7 , wherein the method is implemented in Verilog and conforms to a Universal Verification Methodology.
13. A method for verification of a design of a memory, the method comprising:
using, by a processor-based system, a bit spreading geometry file to convert a logical address of the memory to a physical address, wherein the bit spreading geometry file defines a bit spreading scheme by which data bits of a data word stored at the logical address are stored in a spread fashion over a plurality of random access memories (RAMs) of the memory;
causing, by the processor-based system, a design simulator to simulate a write of a test data word to the logical address of the memory;
reading, by the processor-based system, data bits from the physical address;
arranging, by the processor-based system, the data bits to form a retrieved data word; and
comparing, by the processor-based system, the test data word to the retrieved data word to verify the design of the memory;
wherein the bit spreading geometry file is configured to specify a logical base address of the memory, a size of the memory, and a description of the each of the plurality of RAMs.
14. The method of claim 13 , further comprising:
writing data bits of the test data word to the physical address;
causing the design simulator to simulate a read from the logical address; and
comparing a result of the simulated read to the test data word to further verify the design of the memory.
15. The method of claim 13 , wherein the description of the each of the plurality of RAMs includes a number of blocks of the RAM, a number of bits of each of the blocks of the RAM, and an identifying label of the RAM.
16. The method of claim 13 , wherein the method iterates over additional logical addresses.
17. The method of claim 13 , wherein the design of the memory is represented as a register transfer level description configured for execution by the design simulator and the method is implemented in Verilog and conforms to a Universal Verification Methodology.