Multi-chip package and manufacturing method thereof
A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.
1. A multi-chip package, comprising:
an interposer connection structure having a first surface and a second surface opposite to the first surface and including a conductive pattern, the conductive pattern comprising a first conductive pattern disposed on the first surface of the interposer connection structure;
a conductive post disposed on the first surface of the interposer connection structure and electrically connected to the conductive pattern;
a first lower semiconductor chip and a second lower semiconductor chip disposed side by side on the first surface of the interposer connection structure and electrically connected to the conductive pattern;
a first upper semiconductor chip and a second upper semiconductor chip disposed side by side on the second surface of the interposer connection structure and electrically connected to the conductive pattern;
a first encapsulant disposed on the first surface of the interposer connection structure and encapsulating at least portions of the conductive post, the first lower semiconductor chip, and the second lower semiconductor chip;
a redistribution circuit structure disposed above the first encapsulant; and
a bonding structure bonding the interposer connection structure and one or more of the first lower semiconductor chip, the second lower semiconductor chip, the first upper semiconductor chip, and the second upper semiconductor chip,
wherein the first upper semiconductor chip overlaps with the first lower semiconductor chip and the conductive post in a direction perpendicular to the first surface of the interposer connection structure, and
the second upper semiconductor chip overlaps with the first lower semiconductor chip and the second lower semiconductor chip in the direction perpendicular to the first surface of the interposer connection structure,
wherein the first lower semiconductor chip includes a first lower connection conductor and the second lower semiconductor chip includes a second lower connection conductor,
the first lower connection conductor and the second lower connection conductor are coupled to the first conductive pattern, and
wherein the first lower semiconductor chip is spaced apart from the redistribution circuit structure with the first encapsulant therebetween,
wherein a surface of the second lower semiconductor chip away from the interposer connection structure, a surface of the first encapsulant away from the interposer connection structure, and a surface of the conductive post away from the interposer connection structure are coplanar with each other and directly contact the redistribution circuit structure.
2. The multi-chip package according to claim 1 , wherein the second lower semiconductor chip includes a conductive through-via structure and is electrically connected to the redistribution circuit structure.
3. The multi-chip package according to claim 1 , wherein the conductive pattern further comprises:
a second conductive pattern disposed on the second surface of the interposer connection structure,
a conductive via pattern disposed between the first conductive pattern and the second conductive pattern and connecting the first conductive pattern and the second conductive pattern.
4. The multi-chip package according to claim 3 , wherein a width of the conductive via pattern closer to the second conductive pattern is greater than a width of the conductive via pattern closer to the first conductive pattern.
5. The multi-chip package according to claim 3 , wherein a width of the conductive via pattern closer to the second conductive pattern is smaller than a width of the conductive via pattern closer to the first conductive pattern.
6. The multi-chip package according to claim 3 , wherein the first upper semiconductor chip includes a first upper connection conductor and the second upper semiconductor chip includes a second upper connection conductor, and
the first upper connection conductor and the second upper connection conductor are coupled to the second conductive pattern.
7. The multi-chip package according to claim 1 , wherein the bonding structure includes a bonding metal having a melting point of less than 200° C.
8. The multi-chip package according to claim 1 , wherein at least one of the first upper semiconductor chip and the second upper semiconductor chip includes a conductive through-via structure, and
the multi-chip package further comprises:
a top semiconductor chip located above the first upper semiconductor chip and the second upper semiconductor chip and electrically connected to the conductive through-via structure.