Package structures having underfills
A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.
1. A package structure, comprising:
a lower substrate;
substrate connection terminals on the lower substrate;
a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate;
first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, respectively, as viewed in a plan view, and covering at least one of the substrate connection terminals; and
a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in the plan view.
2. The package structure as claimed in claim 1 , wherein each of the first underfills includes:
an inner portion overlapping the semiconductor package in a vertical direction, the inner portion covering the substrate connection terminals; and
an outer portion not overlapping the semiconductor package in the vertical direction.
3. The package structure as claimed in claim 2 , wherein the outer portion covers side surfaces of the package substrate and the first encapsulant.
4. The package structure as claimed in claim 3 , wherein a height of a portion of the semiconductor package covered by the outer portion is 80% or less of a height of the semiconductor package.
5. The package structure as claimed in claim 2 , wherein an upper end of the outer portion is at a higher level than an upper end of the inner portion.
6. The package structure as claimed in claim 2 , wherein a total area of the inner portions is 40% or less of an area of a bottom of the package substrate.
7. The package structure as claimed in claim 2 , wherein cross-sections of the inner portion and the outer portion are concave.
8. The package structure as claimed in claim 2 , wherein cross-sections of the inner portion and the outer portion are convex.
9. The package structure as claimed in claim 1 , wherein lower surfaces of the first underfills and a lower surface of the second underfill are coplanar.
10. The package structure as claimed in claim 1 , wherein:
a coefficient of thermal expansion (CTE) of the first underfills is greater than a CTE of the second underfill by 50% or more,
a modulus of the first underfills is 50% or less than a modulus of the second underfill,
a filler content of the first underfills is lower than the filler content of the second underfill, and
an elongation of the first underfills is greater than an elongation of the second underfill by 50% or more.
11. The package structure as claimed in claim 10 , wherein:
the CTE of the first underfills is 50 ppm/° C. to 500 ppm/° C.,
the modulus of the first underfills is 1 GPa or less,
the filler content of the first underfill is 40 wt % or less, and
the elongation of the first underfills is 10% or more.
12. The package structure as claimed in claim 11 , wherein:
the CTE of the second underfill is 10 ppm/° C. to 40 ppm/° C.,
the modulus of the second underfill is 5 GPa or more,
the filler content of the second underfill is 45 wt % to 60 wt %, and
the elongation of the second underfill is 5% or less.
13. The package structure as claimed in claim 1 , wherein, in the plan view, a length of a portion of the side surface of the semiconductor package covered by the first underfills is less than ⅓ of a length of the side surface of the semiconductor package.
14. The package structure as claimed in claim 1 , wherein:
the first underfills further include a first extension portion extending in a first horizontal direction and a second extension portion extending in a second horizontal direction crossing the first horizontal direction, and
the first extension portion and the second extension portion partially cover the side surface of the semiconductor package, as viewed in the plan view.
15. The package structure as claimed in claim 1 , further comprising a third underfill between the lower substrate and the semiconductor package, the third underfill partially covering the side surface of the semiconductor package, as viewed in the plan view.
16. A package structure, comprising:
a lower substrate;
substrate connection terminals on the lower substrate;
a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate;
a stiffener on the lower substrate and extending around the semiconductor package;
a heat spreader on the stiffener, the heat spreader being connected to the stiffener and an upper surface of the semiconductor package;
first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals; and
a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package, as viewed in the plan view.
17. The package structure as claimed in claim 16 , further comprising a heat sink on the heat spreader.
18. A package structure, comprising:
a lower substrate including upper pads thereon;
external connection terminals on a lower surface of the lower substrate;
substrate connection terminals connected to the upper pads;
a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate, first semiconductor chips and second semiconductor chips on the package substrate, and a first encapsulant covering the package substrate and the first and second semiconductor chips;
first underfills on the lower substrate, each of the first underfills including:
an inner portion overlapping the semiconductor package in a vertical direction, the inner portion covering at least one of the substrate connection terminals, and
an outer portion not overlapping the semiconductor package in the vertical direction, the outer portion covering a corner portion of the semiconductor package in a plan view, and lower surfaces of the inner portion and the outer portion being coplanar; and
a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in the plan view,
wherein each of the second semiconductor chips includes first to fourth memory chips stacked in the vertical direction, four of the second semiconductor chips being positioned adjacent to each of the first semiconductor chips.
19. The package structure as claimed in claim 18 , further comprising a dummy chip between the first semiconductor chips.
20. The package structure as claimed in claim 19 , wherein the second semiconductor chips further include a second encapsulant covering the first to fourth memory chips.