IP Library › Granted Patent US 11,588,279
Granted Patent B2
US 11,588,279 · App. 17/031,800 · Granted Feb 21, 2023

Dual in-line memory module (DIMM) socket circuit to detect improper insertion of a DIMM edge into a DIMM socket

Inventors: Xiang Li (Portland, OR); George Vergis (Portland, OR)
Assignee: Intel Corporation
H01R13/6683H01R12/737H01R13/635
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Quick Facts
Patent No.
US 11,588,279
App. No.
17/031,800
Granted
Feb 21, 2023
Kind
B2
Abstract

An apparatus is described. The apparatus includes a dual-in line memory module (DIMM) socket having a first electrical circuit component embedded in a latch of the DIMM socket. The first electrical circuit component has a first exposed electrical contact that is to contact or not contact a second exposed electrical contact of a second electrical circuit component that is embedded in a housing of the socket depending on whether a corner of a DIMM is or is not properly inserted into the DIMM socket.

Claims (26)

1. An apparatus, comprising:

a dual-in line memory module (DIMM) socket comprising a first electrical circuit component embedded in a latch of the DIMM socket, the first electrical circuit component having a first exposed electrical contact that is to contact or not contact a second exposed electrical contact of a second electrical circuit component that is embedded in a housing of the socket depending on whether a corner of a DIMM is or is not properly inserted into the DIMM socket.

2. The apparatus of claim 1 wherein the second electrical circuit component extends out of the DIMM socket to form a connection to a motherboard.

3. The apparatus of claim 1 wherein the first electrical circuit component further comprises a third exposed electrical contact that is to contact or not contact a fourth exposed electrical contact of a third electrical circuit component that is embedded in the housing of the socket depending on whether the corner of the DIMM is or is not properly inserted into the DIMM socket.

4. The apparatus of claim 1 wherein the first and second exposed electrical contacts are to make contact when the corner of the DIMM is properly inserted into the DIMM socket.

5. The apparatus of claim 1 wherein the first electrical circuit component is embedded in an ejector of the latch.

6. The apparatus of claim 5 wherein the first electrical circuit component is a pin.

7. The apparatus of claim 6 wherein the first electrical circuit component is embedded in an ejector of the latch and the second and third exposed electrical contacts are positioned to face opposite sides of the latch.

8. A computing system, comprising:

a plurality of processing cores;

a network interface;

a memory controller; and,

a memory coupled to the memory controller, the memory comprising a dual-in line memory module (DIMM) socket comprising a first electrical circuit component embedded in a latch of the DIMM socket, the first electrical circuit component having a first exposed electrical contact that is to contact or not contact a second exposed electrical contact of a second electrical circuit component that is embedded in a housing of the socket depending on whether a corner of a DIMM is or is not properly inserted into the DIMM socket.

9. The computing system of claim 8 wherein the second electrical circuit component extends out of the DIMM socket to form a connection to a motherboard.

10. The computing system of claim 8 wherein the first electrical circuit component further comprises a third exposed electrical contact that is to contact or not contact a fourth exposed electrical contact of a third electrical circuit component that is embedded in the housing of the socket depending on whether the corner of the DIMM is or is not properly inserted into the DIMM socket.

11. The computing system of claim 8 wherein the first and second exposed electrical contacts are to make contact when the corner of the DIMM is properly inserted into the DIMM socket.

12. The computing system of claim 8 wherein the DIMM socket is mounted to a motherboard and the motherboard comprises circuitry coupled to the second electrical circuit component, the circuit to determine whether a closed circuit exists through a circuit formed with the first electrical circuit component and the second electrical circuit component.

13. The computing system of claim 8 wherein the first electrical circuit component is embedded in an ejector of the latch.

14. The computing system of claim 13 wherein the first electrical circuit component is a pin.

15. The computing system of claim 14 wherein the first electrical circuit component is embedded in an ejector of the latch and the second and third exposed electrical contacts are positioned to face opposite sides of the latch.

16. A method, comprising:

detecting if a corner of a dual in line memory module (DIMM) is properly inserted into a DIMM socket by detecting whether an open or closed state exists in a circuit comprising circuit elements formed in the DIMM socket;

wherein the circuit elements comprise a first circuit element that is embedded in a latch of the DIMM socket and a second circuit element that is embedded in a housing of the DIMM socket.

17. The method of claim 16 , wherein the first circuit element is embedded in an ejector of the latch.

18. The method of claim 16 further comprising refusing to send at least one voltage to the DIMM if the corner of the DIMM is not detected to be properly inserted into the DIMM socket.

19. The method of claim 16 further comprising detecting if an opposite corner of the DIMM is properly inserted into the DIMM socket by an open or closed state in a second circuit comprising circuit elements formed in the DIMM socket.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2020
From: LI, XIANG; VERGIS, GEORGE
To: INTEL CORPORATION
Reel/Frame 053879/0164 →
Continuity (1)
Related Publication 20210021089A1 · Jan 21, 2021
Cited By (1)
US 12,315,587