IP Library › Granted Patent US 12,315,587
Granted Patent B2
US 12,315,587 · App. 17/351,556 · Granted May 27, 2025

DIMM socket with seating floor to meet both longer length edge contacts and shorter length edge contacts

Inventors: Xiang Li (Portland, OR); George Vergis (Portland, OR)
Assignee: Intel Corporation
G11C5/025G06F1/185G11C5/06H01R13/11H05K7/1429H05K7/1435
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Quick Facts
Patent No.
US 12,315,587
App. No.
17/351,556
Granted
May 27, 2025
Kind
B2
Abstract

An apparatus is described. The apparatus includes a DIMM socket having a seating floor that is to meet both longer length contacts and shorter length contacts of a DIMM when the DIMM is fully seated in the socket.

Claims (24)

1. An apparatus, comprising:

a dual-in line memory module (DIMM) socket having a seating floor that is to meet both longer length edge contacts and shorter length edge contacts of a DIMM when the DIMM is fully seated in the socket, wherein first and second ones of the shorter length edge contacts are to respectively mate with socket pins having different voltages, and wherein the socket pins are neighboring socket pins.

2. The apparatus of claim 1 wherein the shorter length edge contacts are closer to an outer region of the DIMM's edge contacts and the longer length edge contacts are closer to an inner region of the DIMM's edge contacts.

3. The apparatus of claim 2 wherein the seating floor ramps upward from the inner region to the outer region.

4. The apparatus of claim 1 wherein the DIMM is unable to rotate while within the socket in a manner that damages pins of the socket.

5. The apparatus of claim 1 wherein the DIMM and socket support a dual data rate memory channel.

6. The apparatus of claim 5 wherein the dual data rate memory channel is configured to operate in accordance with a Joint Electron Device Engineering Council (JEDEC) standard to include the JEDEC standard for a Dual Data Rate 5 (DDR5) memory implementation.

7. A computing system, comprising:

a plurality of processing cores;

a network interface;

a memory controller; and,

a memory coupled to the memory controller, the memory comprising a dual-in line memory module (DIMM) socket comprising a seating floor that is to meet both longer length edge contacts and shorter length edge contacts of a DIMM when the DIMM is fully seated in the socket, wherein first and second ones of the shorter length edge contacts are to respectively mate with socket pins having different voltages, and wherein the socket pins are neighboring socket pins.

8. The computing system of claim 7 wherein the shorter length edge contacts are closer to an outer region of the DIMM's edge contacts and the longer length edge contacts are closer to an inner region of the DIMM's edge contacts.

9. The computing system of claim 8 wherein the seating floor ramps upward from the inner region to the outer region.

10. The computing system of claim 7 wherein the DIMM is unable to rotate while within the socket in a manner that damages pins of the socket.

11. The computing system of claim 7 wherein the DIMM and socket support a dual data rate memory channel.

12. The computing system of claim 11 wherein the dual data rate memory channel is configured to operate in accordance with a Joint Electron Device Engineering Council (JEDEC) standard to include the JEDEC standard for a Dual Data Rate 5 (DDR5) memory implementation.

13. A method, comprising:

pressing a dual-in line memory module (DIMM) having longer length edge contacts and shorter length edge contacts into a DIMM socket, the DIMM stopping at a seating floor of the DIMM socket such that both the longer length edge contacts and the shorter length edge contacts meet the seating floor because the seating floor comprises a higher level to meet the shorter length edge contacts and a lower level to meet the longer length edge contacts.

14. The method of claim 13 wherein the shorter length edge contacts are closer to an outer region of the DIMM's edge contacts and the longer length edge contacts are closer to an inner region of the DIMM's edge contacts.

15. The method of claim 13 wherein the DIMM and socket support a dual data rate memory channel.

16. The method of claim 13 wherein the dual data rate memory channel is configured to operate in accordance with a Joint Electron Device Engineering Council (JEDEC) standard to include the JEDEC standard for a Dual Data Rate 5 (DDR5) memory implementation.

17. The method of claim 13 wherein first and second ones of the shorter length edge contacts are to respectively mate with socket pins having different voltages.

18. The method of claim 17 wherein the socket pins are neighboring socket pins.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2021
From: LI, XIANG; VERGIS, GEORGE
To: INTEL CORPORATION
Reel/Frame 056585/0267 →
Continuity (1)
Related Publication 20210312953A1 · Oct 7, 2021
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