Semiconductor storage device

1. A semiconductor storage device, comprising:

a first memory cell electrically connected to a first bit line and a first word line;

a second memory cell electrically connected to a second bit line and the first word line; and

a first circuit configured to supply voltages to the first word line, wherein

during a reading operation to read a page of memory cells including the first memory cell and the second memory cell, while the first memory cell is selected as a read target during a first time period, the first circuit supplies:

a first voltage to the first word line,

a second voltage that is greater than the first voltage to the first word line after supplying the first voltage,

a third voltage that is less than the second voltage to the first word line directly after supplying the second voltage; and

during the reading operation to read the page of memory cells including the first memory cell and the second memory cell, while the second memory cell is selected as the read target during a second time period that is different from the first time period, the first circuit supplies:

the first voltage to the first word line,

the second voltage to the first word line after supplying the first voltage,

a fourth voltage that is less than the third voltage to the first word line directly after supplying the second voltage, and

the third voltage to the first word line directly after supplying the fourth voltage.

2. The semiconductor storage device according to claim 1 , wherein the first voltage and the fourth voltage are not read voltages, the second voltage is a read pass voltage, and the third voltage is a read voltage.

3. The semiconductor storage device according to claim 1 , wherein a distance from the first circuit to the first memory cell is shorter than a distance from the first circuit to the second memory cell.

4. The semiconductor storage device according to claim 1 , wherein, during the reading operation to read the page of the memory cells, while the first memory cell is selected as the read target during the first time period, the first circuit supplies a fifth voltage that is less than the third voltage to the first word line directly after supplying the third voltage.

5. The semiconductor storage device according to claim 4 , wherein, during the reading operation to read the page of the memory cells, while the second memory cell is selected as the read target during the second time period, the first circuit supplies:

a sixth voltage that is less than the fifth voltage to the first word line directly after supplying the third voltage, and

the fifth voltage to the first word line directly after supplying the sixth voltage.

6. The semiconductor storage device according to claim 5 , wherein

the sixth voltage is not a read voltage, and

the fifth voltage is a read voltage.

7. The semiconductor storage device according to claim 5 , wherein

the third voltage is a read voltage at a first voltage level, and

the fifth voltage is a read voltage at a second voltage level that is lower than the first voltage level.

8. The semiconductor storage device according to claim 1 , further comprising:

a third memory cell electrically connected to a third bit line and the first word line, the third bit line being between the first bit line and the second bit line; and

a fourth memory cell electrically connected to a fourth bit line and the first word line, the second bit line being between the third bit line and the fourth bit line, wherein

during the reading operation to read the page of the memory cells, while the first memory cell is selected as the read target during the first time period, the first circuit supplies:

a seventh voltage to the first bit line, and

an eighth voltage to the second bit line, the third bit line, and the fourth bit line, and

during the reading operation to read the page of the memory cells, while the second memory cell is selected as the read target during the second time period, the first circuit supplies:

the seventh voltage to the second bit line, and

the eighth voltage to the first bit line, the third bit line and the fourth bit line.

9. The semiconductor storage device according to claim 8 , wherein the first and third bit lines are adjacent to each other.

10. The semiconductor storage device according to claim 8 , wherein the second and fourth bit lines are adjacent to each other.

11. The semiconductor storage device according to claim 1 , wherein, along the first word line, the first memory cell is between the first circuit and the second memory cell.

12. The semiconductor storage device according to claim 1 , further comprising:

a third memory cell electrically connected to a third bit line and the first word line, the third bit line being adjacent to the first bit line; and

a fourth memory cell electrically connected to a fourth bit line and the first word line, the fourth bit line being adjacent to the second bit line, wherein

during the reading operation to read the page of the memory cells including the third memory cell and the fourth memory cell, while the third memory cell is selected as the read target during a third time period that is different from the first and the second time period, the first circuit supplies:

the first voltage to the first word line,

the second voltage to the first word line after supplying the first voltage,

the third voltage to the first word line directly after supplying the second voltage; and

during the reading operation to read the page of memory cells including the third memory cell and the fourth memory cell, while the fourth memory cell is selected as the read target during a fourth time period that is different from the first, second and the third time periods, the first circuit supplies:

the first voltage to the first word line,

the second voltage to the first word line after supplying the first voltage,

the fourth voltage to the first word line directly after supplying the first voltage, and

the third voltage to the first word line directly after supplying the fourth voltage.

13. The semiconductor storage device according to claim 12 , wherein a distance from the first circuit to the first memory cell is shorter than a distance from the first circuit to the second memory cell.

14. The semiconductor storage device according to claim 1 , wherein a read operation is performed in response to a command sequence including a first command for setting a read unit size.

15. The semiconductor storage device according to claim 1 , wherein a read operation is performed in response to a command sequence including a first command for setting a read unit size and a first address designating a plane and a read region.

16. The semiconductor storage device according to claim 15 , wherein the read unit size is one fourth of all bit lines of a memory cell array in a plane.

17. The semiconductor storage device according to claim 1 , wherein the semiconductor storage device starts a set feature operation in response to a command sequence including a command for changing parameters of the semiconductor storage device.

18. The semiconductor storage device according to claim 17 , wherein

the command sequence further includes an address designating an address corresponding to a read operation parameter to be changed and a value for the read operation parameter to be changed, and

the read operation parameter is a read unit size.

19. The semiconductor storage device according to claim 18 , wherein the read unit size is one fourth of all bit lines of memory cell array in the plane.

20. The semiconductor storage device according to claim 17 , wherein, after the set feature operation ends, the read operation starts in response to another command sequence including a command requesting input of a second address designating an address for reading data.