Three-dimensional semiconductor memory device and electronic system including the same

1. A three-dimensional semiconductor memory device, comprising:

a first structure; and

a second structure in contact with the first structure,

wherein each of the first and second structures comprises:

a substrate;

a peripheral circuit region on the substrate; and

a cell array region comprising a stack structure on the peripheral circuit region, a plurality of vertical structures that penetrate the stack structure, and a common source region in contact with the vertical structures,

wherein the stack structure is between the peripheral circuit region and the common source region,

wherein the common source regions of the first and second structures are connected with each other, and

wherein the three-dimensional semiconductor memory device further comprises a junction conductive layer between the common source region of the first structure and the common source region of the second structure.

2. The three-dimensional semiconductor memory device of claim 1 ,

wherein the peripheral circuit region comprises:

a plurality of peripheral transistors on the substrate; and

a plurality of first bonding pads connected to respective ones of the peripheral transistors,

wherein the cell array region further comprises:

a plurality of bit lines connected to respective ones of the vertical structures;

a plurality of conductive lines spaced apart in a horizontal direction from the bit lines; and

a plurality of second bonding pads connected to the bit lines or the conductive lines, and

wherein each of the first bonding pads is integrally bonded with respective ones of the second bonding pads.

3. The three-dimensional semiconductor memory device of claim 2 , wherein the cell array region further comprises a source conductive pattern between the stack structure and the common source region,

wherein each of the vertical structures is in a respective vertical channel that penetrates the stack structure,

wherein each of the vertical structures comprises:

a data storage pattern that conformally covers an inner wall of the respective vertical channel; and

a vertical semiconductor pattern surrounded by the data storage pattern, and

wherein the source conductive pattern is in contact with a sidewall of the vertical semiconductor pattern.

4. The three-dimensional semiconductor memory device of claim 3 ,

wherein the respective vertical channel comprises a first vertical channel and a second vertical channel connected to the first vertical channel, and

wherein the first vertical channel and the second vertical channel have different diameters at a boundary where the first and second vertical channels are connected to each other.

5. The three-dimensional semiconductor memory device of claim 3 , wherein the cell array region further comprises:

a dielectric layer on the stack structure; and

a common source contact plug that penetrates the dielectric layer and connects one of the conductive lines to the common source region.

6. The three-dimensional semiconductor memory device of claim 5 ,

wherein the cell array region of each of the first and second structures further comprises a peripheral connection contact plug that penetrates the dielectric layer and the common source region and is electrically connected to the peripheral circuit region,

wherein the peripheral connection contact plug is spaced apart from the stack structure, the common source region, and the common source contact plug, and

wherein the peripheral connection contact plug of the first structure and the peripheral connection contact plug of the second structure are in contact with each other.

7. The three-dimensional semiconductor memory device of claim 3 , wherein an overall thickness of the common source regions of the first and second structures, and the source conductive pattern in the first structure and the source conductive pattern in the second structure is about 2 to 4 times a thickness of one of the common source region of the first structure or the common source region of the second structure.

8. The three-dimensional semiconductor memory device of claim 3 , wherein an overall thickness of the common source regions of the first and second structures and the source conductive pattern in the first structure and the source conductive pattern in the second structure is in a range of about 10 kÅ to about 40 kÅ.

9. The three-dimensional semiconductor memory device of claim 1 , wherein the common source region has a plate shape extending parallel to a top surface of the substrate.

10. The three-dimensional semiconductor memory device of claim 1 ,

wherein the stack structure comprises a plurality of interlayer dielectric layers and a plurality of gate electrodes that are alternately stacked and extend in a direction parallel to a top surface of the substrate, and

wherein the gate electrodes have respective lengths that increase with increasing distances of respective ones of the gate electrodes from the substrate.

11. The three-dimensional semiconductor memory device of claim 10 ,

wherein each of the vertical structures has a respective width that increases with increasing distance from the common source region, and

wherein the gate electrodes of the stack structure have respective lengths in the direction that decrease with increasing distances from the common source region.

12. The three-dimensional semiconductor memory device of claim 1 , wherein a thickness of the junction conductive layer is less than a thickness of the common source region of the first structure and the common source region of the second structure.

13. A three-dimensional semiconductor memory device, comprising:

a first structure; and

a second structure in contact with the first structure,

wherein each of the first and second structures comprises:

a substrate;

a peripheral circuit region comprising a plurality of peripheral transistors on the substrate, a plurality of peripheral circuit lines on the peripheral transistors, and a plurality of first bonding pads connected to the peripheral transistors through the peripheral circuit lines; and

a cell array region comprising a plurality of second bonding pads which are integrally bonded with respective ones of the first bonding pads of the peripheral circuit region, a plurality of connection circuit lines on the second bonding pads, a plurality of bit lines connected to the second bonding pads through the connection circuit lines, a stack structure on the bit lines, a plurality of vertical structures that penetrate the stack structure, a common source region in contact with the vertical structures, and a source conductive pattern between the stack structure and the common source region,

wherein the stack structure is between the peripheral circuit region and the common source region,

wherein the common source regions of the first and second structures are connected to each other,

wherein each of the vertical structures is in a respective vertical channel that penetrates the stack structure,

wherein each of the vertical structures comprises a data storage pattern that conformally covers an inner wall of the respective vertical channel and a vertical semiconductor pattern surrounded by the data storage pattern,

wherein the data storage pattern comprises a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer that are sequentially stacked, and

wherein the source conductive pattern is in contact with the vertical semiconductor pattern.

14. The three-dimensional semiconductor memory device of claim 13 ,

wherein the stack structure comprises a plurality of interlayer dielectric layers and a plurality of gate electrodes that are alternately stacked and extend in a direction parallel to a top surface of the substrate, and

wherein the gate electrodes have respective lengths that increase with increasing distance from the substrate.

15. The three-dimensional semiconductor memory device of claim 13 , wherein the first bonding pads and the second bonding pads comprise copper (Cu).

16. The three-dimensional semiconductor memory device of claim 13 ,

wherein the respective vertical channel comprises a first vertical channel and a second vertical channel connected to the first vertical channel, and

wherein the first vertical channel and the second vertical channel have different diameters at a boundary where the first and second vertical channels are connected to each other.

17. The three-dimensional semiconductor memory device of claim 13 ,

wherein the cell array region of each of the first and second structures further comprises a peripheral connection contact plug that penetrates the common source region, and

wherein the peripheral connection contact plug of the first structure and the peripheral connection contact plug of the second structure contact each other and electrically connect the peripheral circuit region of the first structure with the peripheral circuit region of the second structure.

18. An electronic system, comprising:

a three-dimensional semiconductor memory device that comprises a first structure, a second structure, and an input/output pad,

wherein each of the first and second structures comprises:

a substrate;

a peripheral circuit region on the substrate; and

a cell array region comprising a stack structure on the peripheral circuit region, a plurality of vertical structures that penetrate the stack structure, and a common source region in contact with the vertical structures,

wherein the input/output pad is connected to the peripheral circuit region of the second structure; and

a controller that is electrically connected to the three-dimensional semiconductor memory device through the input/output pad and is configured to control the three-dimensional semiconductor memory device,

wherein the stack structure is between the peripheral circuit region and the common source region,

wherein the common source regions of the first and second structures are connected with each other,

wherein the cell array region further comprises a source conductive pattern between the stack structure and the common source region, and

wherein the source conductive pattern is in contact with a sidewall of the vertical structure.

19. The electronic system of claim 18 ,

wherein the peripheral circuit region comprises a plurality of peripheral transistors on the substrate, and a plurality of first bonding pads connected to respective ones of the peripheral transistors,

wherein the cell array region further comprises a plurality of bit lines connected to respective ones of the vertical structures, a plurality of conductive lines spaced apart in a horizontal direction from the bit lines, and a plurality of second bonding pads connected to the bit lines or the conductive lines, and

wherein each of the first bonding pads is integrally bonded with a respective one of the second bonding pads.