Integrated circuit structure and manufacturing method thereof

1. A method comprising:

forming a semiconductor fin over a semiconductor substrate;

depositing a gate electrode layer over the semiconductor substrate;

patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion, wherein patterning the gate electrode layer is performed such that the gate electrode extending portion is over the semiconductor fin;

forming a first gate spacer alongside the first gate electrode;

patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and

forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first gate spacer.

2. The method of claim 1 , wherein forming the second gate spacer and the third gate spacer comprises:

depositing a spacer layer over the semiconductor substrate, the first gate electrode, the first gate spacer, and the second gate electrode; and

patterning the spacer layer into the second gate spacer and the third gate spacer.

3. The method of claim 1 , wherein patterning the gate electrode layer is performed such that the first gate electrode is over a region of the semiconductor substrate free of the semiconductor fin.

4. The method of claim 1 , further comprising:

depositing a filling material on a side of the first gate spacer facing away from the first gate electrode prior to patterning the gate electrode extending portion.

5. The method of claim 4 , further comprising:

removing the filling material after patterning the gate electrode extending portion and prior to forming the second gate spacer.

6. The method of claim 5 , further comprising:

masking the second gate electrode when removing the filling material.

7. A method comprising:

forming a semiconductor fin over a first region of a semiconductor substrate;

forming an isolation structure surrounding the semiconductor fin;

depositing a first dielectric layer over a second region of the semiconductor substrate after forming the isolation structure;

recessing a top surface of the isolation structure to a level lower than a top of the semiconductor fin;

forming a first gate structure over the semiconductor fin; and

forming a second gate structure over the second region of the semiconductor substrate, wherein the second gate structure is larger than the first gate structure from a top view.

8. The method of claim 7 , further comprising:

masking the second region of the semiconductor substrate when recessing the top surface of the isolation structure.

9. The method of claim 7 , further comprising:

forming a well region in the semiconductor fin prior to recessing the top surface of the isolation structure.

10. The method of claim 7 , further comprising:

removing a portion of the first dielectric layer over the first region of the semiconductor substrate prior to recessing the top surface of the isolation structure.

11. The method of claim 7 , wherein recessing the top surface of the isolation structure is performed such that a portion of the first dielectric layer over the first region of the semiconductor substrate is removed.

12. The method of claim 7 , further comprising:

forming a second dielectric layer over the semiconductor fin after recessing the top surface of the isolation structure.

13. An integrated circuit (IC) structure, comprising:

a semiconductor substrate;

a first gate electrode over a first region of the semiconductor substrate;

a first gate spacer alongside the first gate electrode;

a first source/drain feature adjacent to the first gate spacer;

a second gate electrode over a second region of the semiconductor substrate, the second gate electrode being larger than the first gate electrode from a top view;

a second gate spacer alongside the second gate electrode, wherein a width of the second gate spacer is greater than a width of the first gate spacer; and

a second source/drain feature adjacent to the second gate spacer, wherein a first distance between the first gate electrode and the first source/drain feature is less than a second distance between the second gate electrode and the second source/drain feature.

14. The IC structure of claim 13 , further comprising:

a dummy gate electrode over a third region of the semiconductor substrate between the first region and the second region of the semiconductor substrate.

15. The IC structure of claim 14 , further comprising:

an isolation structure between the first region and the second region of the semiconductor substrate, wherein the dummy gate electrode is over the isolation structure.

16. The IC structure of claim 14 , wherein the dummy gate electrode forms a closed loop encircling the second gate electrode and the second source/drain feature.

17. The IC structure of claim 13 , wherein a bottommost surface of the first gate electrode is lower than a bottommost surface of the second gate electrode.

18. The IC structure of claim 13 , wherein the semiconductor substrate comprises a semiconductor fin over the first region, the first gate electrode surrounds the semiconductor fin, and a bottommost surface of the second gate electrode is over a top surface of the second region of the semiconductor substrate.

19. The IC structure of claim 13 , wherein the semiconductor substrate comprises a plurality of semiconductor fins over the first region, the second region of the semiconductor substrate is free of the semiconductor fins.

20. The IC structure of claim 19 , wherein the semiconductor fins are aligned with the second region of the semiconductor substrate from a top view.