Semiconductor memory device and method of fabricating the same
Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a capacitor that includes a bottom electrode, a top electrode opposite to the bottom electrode across a dielectric layer, and an interface layer between the bottom electrode and the dielectric layer. The interface layer includes a combination of niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N), and further includes a constituent of the dielectric layer.
1. A semiconductor memory device comprising:
a substrate;
a capacitor bottom electrode disposed over the substrate and including titanium nitride;
a first interface layer disposed on the capacitor bottom electrode;
a capacitor dielectric layer disposed on the first interface layer and including hafnium oxide; and
a capacitor top electrode disposed on the capacitor dielectric layer,
wherein the first interface layer includes a combination of hafnium (Hf), niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N).
2. The semiconductor memory device of claim 1 , wherein the first interface layer includes HfNbTiON.
3. The semiconductor memory device of claim 1 , further comprises a second interface layer that is disposed between the capacitor dielectric layer and the capacitor top electrode.
4. The semiconductor memory device of claim 3 , wherein the second interface layer includes a combination of titanium (Ti), oxygen (O), and nitrogen (N).
5. The semiconductor memory device of claim 3 , wherein the second interface layer includes a combination of niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N).
6. The semiconductor memory device of claim 5 , wherein niobium (Nb) contained in the second interface layer has an amount of about 5 at % or less, narrowly about 2 at % to about 3 at %.
7. The semiconductor memory device of claim 3 , wherein the second interface layer includes a combination of niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N), and a metallic constituent of the capacitor dielectric layer.
8. The semiconductor memory device of claim 1 , wherein niobium (Nb) contained in the first interface layer has an amount of about 5 at % or less, narrowly about 2 at % to about 3 at %.
9. The semiconductor memory device of claim 1 , wherein the capacitor top electrode includes titanium nitride.
10. The semiconductor memory device of claim 1 , wherein the capacitor dielectric layer includes zirconium oxide.
11. The semiconductor memory device of claim 1 , further comprises a support pattern that contacts a side surface of the capacitor bottom electrode, and
wherein the first interface layer is spaced apart from the side surface of the capacitor bottom electrode.
12. A semiconductor memory device comprising:
a substrate;
a capacitor bottom electrode disposed over the substrate and including titanium nitride;
a first interface layer disposed on the capacitor bottom electrode;
a capacitor dielectric layer disposed on the first interface layer and including hafnium oxide and zirconium oxide;
a second interface layer disposed on the capacitor dielectric layer; and
a capacitor top electrode disposed on the second interface layer and including titanium nitride,
wherein the first interface layer includes a combination of hafnium (Hf), niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N), and
the second interface layer includes a combination of titanium (Ti), oxygen (O), and nitrogen (N).
13. The semiconductor memory device of claim 12 , wherein the first interface layer includes HfNbTiON.
14. The semiconductor memory device of claim 12 , wherein niobium (Nb) contained in the first interface layer has an amount of about 5 at % or less, narrowly about 2 at % to about 3 at %.
15. The semiconductor memory device of claim 12 , further comprises a support pattern that contacts a side surface of the capacitor bottom electrode, and
wherein the first interface layer is spaced apart from the side surface of the capacitor bottom electrode.
16. A semiconductor memory device comprising:
a substrate;
a capacitor bottom electrode disposed over the substrate and including titanium nitride;
a first interface layer disposed on the capacitor bottom electrode;
a capacitor dielectric layer disposed on the first interface layer and including hafnium oxide and zirconium oxide;
a second interface layer disposed on the capacitor dielectric layer; and
a capacitor top electrode disposed on the second interface layer and including titanium nitride,
wherein the first interface layer includes a combination of hafnium (Hf), niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N), and
the second interface layer includes a combination of niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N).
17. The semiconductor memory device of claim 16 , wherein the first interface layer includes HfNbTiON.
18. The semiconductor memory device of claim 16 , wherein niobium (Nb) contained in the first interface layer has an amount of about 5 at % or less, narrowly about 2 at % to about 3 at %.
19. The semiconductor memory device of claim 16 , wherein niobium (Nb) contained in the second interface layer has an amount of about 5 at % or less, narrowly about 2 at % to about 3 at %.
20. The semiconductor memory device of claim 16 , further comprises a support pattern that contacts a side surface of the capacitor bottom electrode, and
wherein the first interface layer is spaced apart from the side surface of the capacitor bottom electrode.