Semiconductor device having buried gate structure and method for fabricating the same
Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the semiconductor device includes a substrate, a first doped region and a second doped region formed to be spaced apart from each other by a trench in the substrate, a first gate dielectric layer over the trench, a lower gate over the first gate dielectric layer, an upper gate over the lower gate and having a smaller width than the lower gate, and a second gate dielectric layer between the upper gate and the first gate dielectric layer.
1. A method for fabricating a semiconductor device comprising:
forming a trench in a substrate;
forming a first gate dielectric layer over the trench;
forming a lower gate over the first gate dielectric layer;
forming a second gate dielectric layer covering the first gate dielectric layer;
forming an upper gate over the second gate dielectric layer and the lower gate; and
implanting a dipole inducing material into the second gate dielectric layer before the forming of the upper gate.
2. The method of claim 1 , wherein the forming of the second gate dielectric layer comprises:
forming a dielectric material over the first gate dielectric layer and the lower gate; and
etching the dielectric material to remain as a spacer covering the first gate dielectric layer.
3. The method of claim 1 , wherein the first and second gate dielectric layers comprise the same material.
4. The method of claim 1 , wherein the first and second gate dielectric layers comprise silicon oxide, silicon nitride, a high-k material or combinations thereof.
5. The method of claim 1 , wherein the forming of the lower gate comprises:
forming a first barrier material on the first gate dielectric layer;
forming a first conductive material, filling the trench, on the first barrier material; and
recessing the first conductive material and the first barrier material to form a first gate electrode and a first barrier layer.
6. The method of claim 1 , wherein the forming of the upper gate comprises:
selectively forming a second barrier layer on the lower gate;
forming a second conductive material, filling the trench, on the second barrier layer; and
recessing the second conductive material to form a second gate electrode.
7. The method of claim 6 , wherein the selectively forming of the second barrier layer on the lower gate includes depositing a barrier material including a covering portion that covers a top surface of the lower gate and a dummy portion that partially covers the second gate dielectric layer,
wherein the barrier material is non-conformally deposited so that the covering portion and the dummy portion do not contact each other.
8. The method of claim 7 , wherein the selectively forming of the second barrier layer on the lower gate is performed by physical vapor deposition (PVD).
9. The method of claim 6 , wherein the selectively forming of the second barrier layer on the lower gate comprises selectively performing a plasma treatment on a top surface of the lower gate.
10. The method of claim 9 , wherein the plasma treatment comprises plasma nitridation.
11. The method of claim 1 , wherein the implanting of the dipole inducing material into the second gate dielectric layer comprises:
forming a sacrificial material including the dipole inducing material to cover the second gate dielectric layer and the lower gate;
performing an annealing process to diffuse the dipole inducing material into the second gate dielectric layer; and
removing the sacrificial material.
12. The method of claim 11 , further comprising forming a sacrificial liner to cover the second gate dielectric layer and the lower gate before the forming of the sacrificial material.
13. The method of claim 12 , wherein the sacrificial liner comprises metal nitride.
14. The method of claim 1 , wherein the dipole inducing material is located at an interface between the upper gate and the second gate dielectric layer.
15. The method of claim 1 , wherein the dipole inducing material is located at an interface between the second gate dielectric layer and the first gate dielectric layer.
16. The method of claim 1 , wherein the dipole inducing material comprises a material that decreases a work function value of the upper gate.
17. The method of claim 1 , wherein the dipole inducing material comprises lanthanum.
18. The method of claim 1 , wherein each of the first and second gate dielectric layers comprises silicon oxide, and the dipole inducing material comprises lanthanum-containing silicon oxide.