IP Library Granted Patent US 11,605,440
Granted Patent B2
US 11,605,440 · App. 17/349,358 · Granted Mar 14, 2023

Memory system

Inventors: Naomi Takeda (Yokohama, JP); Masanobu Shirakawa (Chigasaki, JP)
Assignee: Kioxia Corporation
G11C29/42G11C29/18G11C29/44G11C2029/1202G11C2029/1204
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Quick Facts
Patent No.
US 11,605,440
App. No.
17/349,358
Granted
Mar 14, 2023
Kind
B2
Abstract

According to one embodiment, a non-volatile memory includes a plurality of groups and a memory controller configured to execute a first operation. Each of the plurality of groups includes a plurality of cell units. Each of the plurality of cell units includes a plurality of memory cells. The first operation includes: based on a first correction amount associated with a target group, reading data from the target group; and updating the first correction amount to a second correction amount based on the data. The memory controller is configured to: select a first group as the target group; and when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group.

Claims (55)

1. A memory system, comprising:

a non-volatile memory including a plurality of groups, each of the plurality of groups including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells; and

a memory controller configured to execute a first operation,

wherein the first operation includes:

based on a first correction amount associated with a target group, reading data from the target group; and

updating the first correction amount to a second correction amount based on the data, and

wherein the memory controller is configured to:

select a first group as the target group; and

when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group.

2. The memory system according to claim 1 ,

wherein the condition includes reading data from a first cell unit included in the first group based on a read request received from a host device, and

wherein the memory controller is configured to update the first correction amount to the second correction amount based on data read from the first cell unit using the first correction amount, when the condition is satisfied.

3. The memory system according to claim 2 ,

wherein the condition includes receiving, from the host device, a read request for a second cell unit which is included in the first group and is different from the first cell unit, and

wherein when the condition is satisfied, the memory controller is configured to:

calculate a third correction amount based on the first correction amount; and

update the first correction amount to the second correction amount based on data read from the second cell unit using the third correction amount.

4. The memory system according to claim 1 , wherein the condition includes a number of requests received from a host device being equal to or greater than a first threshold.

5. The memory system according to claim 1 , wherein the condition includes the memory system starting to transition from a first state to a second state.

6. The memory system according to claim 5 , wherein:

the first state is an active state; and

the second state is a standby state.

7. The memory system according to claim 5 , wherein:

the first state is an active state; and

the second state is a power-off state.

8. The memory system according to claim 1 ,

wherein satisfying the condition includes satisfying a first condition or a second condition, and

wherein the memory controller is configured to:

in a case where the first condition is satisfied when the first group is selected as the target group, select the second group as the target group after performing the first operation related to the first group, and

in a case where the second condition is satisfied when a third group is selected as the target group, select a fourth group as the target group after performing the first operation related to the third group.

9. The memory system according to claim 8 , wherein when a number of times the first operation related to the first group is executed is equal to or greater than a second threshold, the memory controller is configured to change a condition for executing the first operation related to the first group from the first condition to the second condition.

10. The memory system according to claim 8 , wherein:

the first condition includes the memory system starting to transition from a first state to a second state; and

the second condition includes the memory system starting to transition from the first state to a third state.

11. The memory system according to claim 10 , wherein:

the first state is an active state;

the second state is a first standby state; and

the third state is a second standby state in which a frequency of occurrence is lower than that in the first standby state.

12. The memory system according to claim 11 , wherein when a number of times the first operation related to the first group is executed is equal to or greater than a second threshold, the memory controller is configured to change a condition for executing the first operation related to the first group from the first condition to the second condition.

13. The memory system according to claim 1 , wherein each of the plurality of groups is a unit for erasing data.

14. The memory system according to claim 13 , wherein each of the plurality of cell units is a unit for writing data.

15. The memory system according to claim 14 , wherein the plurality of memory cells in a single cell unit among the plurality of cell units are commonly connected to a same word line, and respectively connected to different bit lines.

16. A memory system, comprising:

a non-volatile memory including a plurality of groups, each of the plurality of groups including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells; and

a memory controller configured to execute a first operation,

wherein the first operation includes:

based on a first correction amount associated with a target group, reading data from the target group; and

updating the first correction amount to a second correction amount based on the data, and

wherein when a condition related to a first group is satisfied, the memory controller is configured to:

select the first group as the target group; and

execute the first operation related to the first group.

17. The memory system according to claim 16 , wherein the condition includes a number of read commands issued for the first group reaching a first number.

18. The memory system according to claim 16 , wherein:

the memory controller is configured to select a first address in the first group; and

the condition includes an address included in a read command for the first group matching the first address.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2021
From: TAKEDA, NAOMI; SHIRAKAWA, MASANOBU
To: KIOXIA CORPORATION
Reel/Frame 056955/0105 →
Priority Claims (1)
JP JP2021-039433 · Mar 11, 2021 · national
Continuity (1)
Related Publication 20220293204A1 · Sep 15, 2022
Cited By (1)
US 12,437,830