Memory system
According to one embodiment, a non-volatile memory includes a plurality of groups and a memory controller configured to execute a first operation. Each of the plurality of groups includes a plurality of cell units. Each of the plurality of cell units includes a plurality of memory cells. The first operation includes: based on a first correction amount associated with a target group, reading data from the target group; and updating the first correction amount to a second correction amount based on the data. The memory controller is configured to: select a first group as the target group; and when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group.
1. A memory system, comprising:
a non-volatile memory including a plurality of groups, each of the plurality of groups including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells; and
a memory controller configured to:
execute a first operation in response to a first read request from a host device, the first read request specifying a first logical address corresponding to a first cell unit included in a target group of the plurality of groups; and
execute a second operation in response to a second read request from the host device, the second read request specifying a second logical address corresponding to a second cell unit different from the first cell unit included in the target group, wherein
the first operation includes:
based on a first correction amount associated with the target group, reading first data from the first cell unit;
executing error correction on the first data;
calculating a second correction amount based on the first data and error-corrected first data; and
updating the first correction amount to the second correction amount, and
the second operation includes:
reading second data from the second cell unit;
executing error correction on the second data;
calculating a third correction amount based on the second data and error-corrected second data;
converting the third correction amount into a fourth correction amount; and
updating the first correction amount to the fourth correction amount.
2. The memory system according to claim 1 , wherein the second operation includes using conversion information to convert the third correction amount into the fourth correction amount.
3. The memory system according to claim 2 , wherein the second operation includes:
converting the first correction amount into a fifth correction amount; and
reading second data from the second cell unit based on the fifth correction amount.
4. The memory system according to claim 3 , wherein the second operation includes using the conversion information to convert the first correction amount into the fifth correction amount.
5. The memory system according to claim 1 , wherein
the target group is a first group of the plurality of groups, and
the memory controller is configured to select a second group different from the first group as the target group when executing the first operation or the second operation.
6. The memory system according to claim 1 , wherein
the target group is a first group of the plurality of groups, and
the memory controller is configured to select a second group different from the first group as the target group when a number of requests received from the host device being equal to or greater than a first threshold.
7. The memory system according to claim 1 , wherein
the target group is a first group of the plurality of groups, and
the memory controller is configured to select a second group different from the first group as the target group when the memory system transits from a first state to a second state.
8. The memory system according to claim 7 , wherein:
the first state is an active state; and
the second state is a standby state.
9. The memory system according to claim 7 , wherein:
the first state is an active state; and
the second state is a power-off state.
10. The memory system according to claim 1 , wherein each of the plurality of groups is a unit for erasing data.
11. The memory system according to claim 10 , wherein each of the plurality of groups is a block.
12. The memory system according to claim 1 , wherein
each of the plurality of cell units includes a word line connected to the plurality of memory cells, and
a second first word line connected to the plurality of memory cells of the second cell unit is different from a first word line connected to the plurality of memory cells of the first cell unit.
13. The memory system according to claim 12 , wherein
each of the plurality of cell units corresponds to a plurality of pages, and
each of the plurality of pages is a unit for writing data.
14. The memory system according to claim 13 , wherein
the first logical address corresponds to one of the plurality of pages corresponding to the first cell unit, and
the second logical address corresponds to one of the plurality of pages corresponding to the second cell unit.
15. The memory system according to claim 14 , wherein
the memory controller is configured to read data from a third cell unit included in a third group of the plurality of groups in response to a third read request from the host device,
the third read request specifies a third logical address,
the third logical address corresponds to one of the plurality of pages corresponding to the third cell unit, and
the third group is different from the target group.
16. The memory system according to claim 15 , wherein
the memory controller is configured to read data from the third cell unit based on a sixth correction amount associated with the third group.
17. The memory system according to claim 16 , wherein
the memory controller is configured to read data from a fourth cell unit included in the third group in response to a fourth read request from the host device,
the fourth read request specifies a fourth logical address,
the fourth logical address corresponds to one of the plurality of pages corresponding to the fourth cell unit, and
the fourth cell unit is different from the third cell unit.
18. The memory system according to claim 17 , wherein
the memory controller is configured to
calculate a seventh correction amount based on the sixth correction amount, and
read data from the fourth cell unit based on the seventh correction amount.
19. The memory system according to claim 18 , wherein the memory controller is configured to use conversion information and to convert the sixth correction amount into the seventh correction amount to calculate the seventh correction amount.
20. The memory system according to claim 16 , wherein the sixth correction amount is a representative correction amount corresponding to the third group.