IP Library Granted Patent US 12,068,049
Granted Patent B2
US 12,068,049 · App. 18/163,906 · Granted Aug 20, 2024

Memory system

Inventors: Naomi Takeda (Yokohama, JP); Masanobu Shirakawa (Chigasaki, JP)
Assignee: Kioxia Corporation
G11C29/42G11C29/18G11C29/44G11C2029/1202G11C2029/1204
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,068,049
App. No.
18/163,906
Granted
Aug 20, 2024
Kind
B2
Abstract

According to one embodiment, a non-volatile memory includes a plurality of groups and a memory controller configured to execute a first operation. Each of the plurality of groups includes a plurality of cell units. Each of the plurality of cell units includes a plurality of memory cells. The first operation includes: based on a first correction amount associated with a target group, reading data from the target group; and updating the first correction amount to a second correction amount based on the data. The memory controller is configured to: select a first group as the target group; and when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group.

Claims (56)

1. A memory system, comprising:

a non-volatile memory including a plurality of groups, each of the plurality of groups including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells; and

a memory controller configured to control the non-volatile memory, wherein

the memory controller is configured to execute a first operation, the first operation including:

based on a first correction amount associated with a target group, reading data from the target group;

executing error correction on the read data;

calculating a second correction amount based on the read data and the read data after the error correction; and

updating the first correction amount to the second correction amount,

the memory controller is configured to select a first group of the plurality of groups as the target group, and

in response to a read request specifying a logical address corresponding to a first cell unit included in the first group, the memory controller is further configured to

read data from the first cell unit based on the first correction amount,

execute the error correction on the read data from the first cell unit, and

calculate the second correction amount based on the read data from the first cell unit and the read data from the first cell unit after the error correction.

2. The memory system according to claim 1 , wherein in response to a read request specifying a logical address corresponding to a second cell unit included in the first group, the second cell unit being different from the first cell unit, the memory controller is further configured to;

calculate a third correction amount based on the first correction amount,

read data from the second cell unit based on the calculated third correction amount,

execute the error correction on the read data from the second cell unit,

calculate a fourth correction amount based on the read data from the second cell unit and the read data from the second cell unit after the error correction, and

calculate the second correction amount based on the fourth correction amount.

3. The memory system according to claim 1 , wherein the memory controller is further configured to select a second group as the target group after performing the first operation related to the first group when a condition is satisfied.

4. The memory system according to claim 3 , wherein the condition includes a number of requests received from a host device being equal to or greater than a first threshold.

5. The memory system according to claim 3 , wherein the condition includes the memory system starting to transition from a first state to a second state.

6. The memory system according to claim 5 , wherein:

the first state is an active state; and

the second state is a standby state.

7. The memory system according to claim 5 , wherein:

the first state is an active state; and

the second state is a power-off state.

8. The memory system according to claim 3 ,

wherein satisfying the condition includes satisfying a first condition or a second condition, and

wherein the memory controller is further configured to:

in a case where the first condition is satisfied when the first group is selected as the target group, select the second group as the target group after performing the first operation related to the first group, and

in a case where the second condition is satisfied when a third group is selected as the target group, select a fourth group as the target group after performing the first operation related to the third group.

9. The memory system according to claim 8 , wherein when a number of times the first operation related to the first group is executed is equal to or greater than a second threshold, the memory controller is further configured to change a condition for executing the first operation related to the first group from the first condition to the second condition.

10. The memory system according to claim 8 , wherein:

the first condition includes the memory system starting to transition from a first state to a second state; and

the second condition includes the memory system starting to transition from the first state to a third state.

11. The memory system according to claim 10 , wherein:

the first state is an active state;

the second state is a first standby state; and

the third state is a second standby state in which a frequency of occurrence is lower than that in the first standby state.

12. The memory system according to claim 11 , wherein when a number of times the first operation related to the first group is executed is equal to or greater than a second threshold, the memory controller is further configured to change a condition for executing the first operation related to the first group from the first condition to the second condition.

13. The memory system according to claim 1 , wherein each of the plurality of groups is a unit for erasing data.

14. The memory system according to claim 13 , wherein each of the plurality of cell units is a unit for writing data.

15. The memory system according to claim 14 , wherein the plurality of memory cells in a single cell unit among the plurality of cell units are commonly connected to a same word line, and respectively connected to different bit lines.

16. A memory system, comprising:

a non-volatile memory including a plurality of groups, each of the plurality of groups including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells; and

a memory controller configured to control the non-volatile memory, wherein

the memory controller is configured to execute a first operation, the first operation including:

based on a first correction amount associated with a target group, reading data from the target group;

executing error correction on the read data;

calculating a second correction amount based on the read data and the read data after the error correction; and

updating the first correction amount to the second correction amount,

the memory controller is configured to select a first group of the plurality of groups as the target group,

the memory controller is further configured to select a second group as the target group after performing the first operation related to the first group when a condition is satisfied, and

the condition includes a number of requests received from a host device being equal to or greater than a first threshold.

Priority Claims (1)
JP 2021-039433 · Mar 11, 2021 · national
Continuity (2)
Continuation 17349358 · Jun 16, 2021
Related Publication 20230187008A1 · Jun 15, 2023
Cited By (1)
US 12,437,830