Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls
Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.
1. An integrated circuit structure, comprising:
an I/O region having a first plurality of semiconductor fins above a substrate and protruding through an uppermost surface of a trench isolation layer;
a logic region having a first logic device and a second logic device, the first logic device having a second plurality of semiconductor fins above the substrate and protruding through the uppermost surface of the trench isolation layer, and the second logic device having a third plurality of semiconductor fins above the substrate and protruding through the uppermost surface of the trench isolation layer;
a first unidirectional gate endcap isolation structure between the I/O region and the first logic device of the logic region, wherein a semiconductor fin of the first plurality of semiconductor fins of the I/O region closest to a first side of the first unidirectional gate endcap isolation structure is spaced farther from the first unidirectional gate endcap isolation structure than a semiconductor fin of the second plurality of semiconductor fins of the first logic device closest to a second side of the first unidirectional gate endcap isolation structure; and
a second unidirectional gate endcap isolation structure between the first logic device of the logic region and the second logic device of the logic region, wherein the second unidirectional gate endcap isolation structure is wider than the first unidirectional gate endcap isolation structure.
2. The integrated circuit structure of claim 1 , wherein the first unidirectional gate endcap isolation structure and the second unidirectional gate endcap isolation structure are in corresponding recesses below the uppermost surface of the trench isolation layer.
3. The integrated circuit structure of claim 1 , wherein the first unidirectional gate endcap isolation structure and the second unidirectional gate endcap isolation structure each comprise a lower dielectric portion and a dielectric cap on the lower dielectric portion.
4. The integrated circuit structure of claim 1 , wherein the second unidirectional gate endcap isolation structure comprises a vertical seam centered within the second unidirectional gate endcap isolation structure.
5. The integrated circuit structure of claim 1 , wherein the first unidirectional gate endcap isolation structure has a total composition different than a total composition of the second unidirectional gate endcap isolation structure.
6. The integrated circuit structure of claim 1 , further comprising:
a local interconnect on the second unidirectional gate endcap isolation structure and electrically coupling the first logic device and the second logic device of the logic region.
7. The integrated circuit structure of claim 6 , wherein the local interconnect is isolated from the I/O region by a dielectric plug.
8. A method of fabricating an integrated circuit structure, the method comprising:
forming an I/O region having a first plurality of semiconductor fins above a substrate and protruding through an uppermost surface of a trench isolation layer;
forming a logic region having a first logic device and a second logic device, the first logic device having a second plurality of semiconductor fins above the substrate and protruding through the uppermost surface of the trench isolation layer, and the second logic device having a third plurality of semiconductor fins above the substrate and protruding through the uppermost surface of the trench isolation layer;
forming a first unidirectional gate endcap isolation structure between the PO region and the first logic device of the logic region, wherein a semiconductor fin of the first plurality of semiconductor fins of the I/O region closest to a first side of the first unidirectional gate endcap isolation structure is spaced farther from the first unidirectional gate endcap isolation structure than a semiconductor fin of the second plurality of semiconductor fins of the first logic device closest to a second side of the first unidirectional gate endcap isolation structure; and
forming a second unidirectional gate endcap isolation structure between the first logic device of the logic region and the second logic device of the logic region, wherein the second unidirectional gate endcap isolation structure is wider than the first unidirectional gate endcap isolation structure.
9. The method of claim 8 , wherein the first unidirectional gate endcap isolation structure and the second unidirectional gate endcap isolation structure are in corresponding recesses below the uppermost surface of the trench isolation layer.
10. The method of claim 8 , wherein the first unidirectional gate endcap isolation structure and the second unidirectional gate endcap isolation structure each comprise a lower dielectric portion and a dielectric cap on the lower dielectric portion.
11. The method of claim 8 , wherein the second unidirectional gate endcap isolation structure comprises a vertical seam centered within the second unidirectional gate endcap isolation structure.
12. The method of claim 8 , wherein the first unidirectional gate endcap isolation structure has a total composition different than a total composition of the second unidirectional gate endcap isolation structure.
13. The method of claim 8 , further comprising:
forming a local interconnect on the second unidirectional gate endcap isolation structure and electrically coupling the first logic device and the second logic device of the logic region.
14. The method of claim 13 , wherein the local interconnect is isolated from the I/O region by a dielectric plug.
15. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
an I/O region having a first plurality of semiconductor fins above a substrate and protruding through an uppermost surface of a trench isolation layer;
a logic region having a first logic device and a second logic device, the first logic device having a second plurality of semiconductor fins above the substrate and protruding through the uppermost surface of the trench isolation layer, and the second logic device having a third plurality of semiconductor fins above the substrate and protruding through the uppermost surface of the trench isolation layer;
a first unidirectional gate endcap isolation structure between the I/O region and the first logic device of the logic region, wherein a semiconductor fin of the first plurality of semiconductor fins of the I/O region closest to a first side of the first unidirectional gate endcap isolation structure is spaced farther from the first unidirectional gate endcap isolation structure than a semiconductor fin of the second plurality of semiconductor fins of the first logic device closest to a second side of the first unidirectional gate endcap isolation structure; and
a second unidirectional gate endcap isolation structure between the first logic device of the logic region and the second logic device of the logic region, wherein the second unidirectional gate endcap isolation structure is wider than the first unidirectional gate endcap isolation structure.
16. The computing device of claim 15 , further comprising:
a memory coupled to the board.
17. The computing device of claim 15 , further comprising:
a communication chip coupled to the board.
18. The computing device of claim 15 , further comprising:
a battery coupled to the board.
19. The computing device of claim 15 , wherein the component is a packaged integrated circuit die.
20. The computing device of claim 15 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.