Memory stacks having silicon nitride gate-to-gate dielectric layers and methods for forming the same

1. A three-dimensional (3D) memory device, comprising:

a memory stack comprising a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers, wherein each of the gate-to-gate dielectric layers comprises at least one silicon oxynitride layer and at least one silicon oxide layer, and in each of the gate-to-gate dielectric layers, a surface of the at least one silicon oxynitride layer being fully covered by the at least one silicon oxide layer along a lateral direction; and

a NAND memory string extending vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack, the lateral direction being perpendicular to a vertical direction that the NAND memory string extends,

wherein:

each of the gate conductive layers comprises a doped polysilicon layer;

the memory stack comprises a first memory deck, a second memory deck above the first memory deck, and an inter-deck dielectric layer between the first memory deck and the second memory deck, the inter-deck dielectric layer comprising a same material as the gate-to-gate dielectric layers and being in direct contact with the first memory deck and the second memory deck; and

the inter-deck dielectric layer fully covers a top surface of the first memory deck and a bottom surface of the second memory deck, and a portion of the inter-deck dielectric layer that is in direct contact with a sidewall of a channel plug extends continuously along the lateral direction to have direct contact with a slit structure.

2. The 3D memory device of claim 1 , wherein the NAND memory string comprises a first channel structure extending vertically through the first memory deck, a second channel structure extending vertically through the second memory deck, and an inter-deck plug vertically between and in contact with the first channel structure and the second channel structure, respectively, wherein the inter-deck plug is above the first channel structure, and is surrounded and isolated from the inter-deck dielectric layer by the second channel structure.

3. The 3D memory device of claim 1 , wherein each of the gate-to-gate dielectric layers comprises a silicon oxynitride layer and a pair of silicon oxide layers, the silicon oxynitride layer being between the pair of silicon oxide layers, and in each of the gate-to-gate dielectric layers, a top surface of the silicon oxynitride layer being fully covered by one of the silicon oxide layers, and a bottom surface of the silicon oxynitride layer being fully covered by another of the silicon oxide layers, along the lateral direction.

4. A three-dimensional (3D) memory device, comprising:

a memory stack comprising a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers, wherein each of the gate-to-gate dielectric layers comprises at least one silicon oxide layer and at least one silicon oxynitride layer; and

a NAND memory string extending vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack,

wherein:

the memory stack comprises a first memory deck, a second memory deck above the first memory deck, and an inter-deck dielectric layer between and in direct contact with the first memory deck and the second memory deck;

the NAND memory string comprises a first channel structure extending vertically through the first memory deck, a second channel structure extending vertically through the second memory deck, and an inter-deck plug vertically between and in contact with the first channel structure and the second channel structure;

the inter-deck dielectric layer fully covers a top surface of the first memory deck and a bottom surface of the second memory deck; and

a slit structure extends vertically through the first memory deck and the second memory deck, and a portion of the inter-deck dielectric layer that is in direct contact with a sidewall of a channel plug extends continuously along a lateral direction to have direct contact with the slit structure, the lateral direction being perpendicular to a vertical direction that the NAND memory string extends.

5. The 3D memory device of claim 4 , wherein each of the gate conductive layers comprises a doped polysilicon layer.

6. The 3D memory device of claim 4 , wherein each of the gate conductive layers comprises a metal layer.

7. A three-dimensional (3D) memory device, comprising:

a substrate;

a memory stack comprising a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers above the substrate, wherein each of the gate-to-gate dielectric layers comprises at least one silicon oxynitride layer and at least one silicon oxide layer, and in each of the gate-to-gate dielectric layers, a surface of the at least one silicon oxynitride layer being fully covered by the at least one silicon oxide layer along a lateral direction; and

a NAND memory string extending vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack, the lateral direction being perpendicular to a vertical direction that the NAND memory string extends,

wherein:

the memory stack comprises a first memory deck above the substrate, a second memory deck above the first memory deck, and an inter-deck dielectric layer between and in direct contact with each of the first memory deck and the second memory deck,

the NAND memory string comprises a first channel structure extending vertically through the first memory deck, a second channel structure extending vertically through the second memory deck, a channel plug in an upper portion of the first channel structure, and an inter-deck plug above and in contact with the channel plug and the second channel structure, the inter-deck plug being surrounded by the second channel structure, and the channel plug being in direct contact with and surrounded by the inter-deck dielectric layer;

a slit structure extends vertically through the memory stack and comprises a spacer on a sidewall of the slit structure and extending into the substrate; and

a portion of the inter-deck dielectric layer that is in direct contact with a sidewall of the channel plug extends continuously along the lateral direction to have direct contact with the spacer of the slit structure.

8. The 3D memory device of claim 7 , wherein each of the gate conductive layers comprises a doped polysilicon layer.

9. The 3D memory device of claim 7 , wherein each of the gate conductive layers comprises a metal layer.

10. The 3D memory device of claim 7 , wherein the inter-deck plug is vertically between and in contact with the first channel structure and the second channel structure, respectively, and is between the first memory deck and the second memory deck.

11. The 3D memory device of claim 4 , wherein the NAND memory string further comprises the channel plug in an upper portion of the first channel structure, the channel plug comprising a different material from a material of the inter-deck plug, and being in contact with the inter-deck dielectric layer on a lateral surface and a vertical surface.

12. The 3D memory device of claim 11 , wherein a lateral dimension of the channel plug is greater than that of the inter-deck plug.

13. The 3D memory device of claim 2 , wherein the inter-deck plug comprises at least one of amorphous silicon, polysilicon, or single-crystal silicon.

14. The 3D memory device of claim 4 , wherein the inter-deck plug comprises single crystal silicon.

15. The 3D memory device of claim 2 , wherein:

the first memory deck extends from a first one of the gate conductive layers intersecting with the first channel structure to a last one of the gate-to-gate dielectric layers intersecting with the first channel structure; and

the second memory deck extends from a top surface of the NAND memory string to a last one of the gate conductive layers intersecting with the second channel structure.

16. The 3D memory device of claim 4 , wherein:

the first memory deck extends from a first one of the gate conductive layers intersecting with the first channel structure to a last one of the gate-to-gate dielectric layers intersecting with the first channel structure; and

the second memory deck extends from a top surface of the NAND memory string to a last one of the gate conductive layers intersecting with the second channel structure.

17. The 3D memory device of claim 7 , wherein:

the first memory deck extends from a first one of the gate conductive layers intersecting with the first channel structure to a last one of the gate-to-gate dielectric layers intersecting with the first channel structure; and

the second memory deck extends from a top surface of the NAND memory string to a last one of the gate conductive layers intersecting with the second channel structure.

18. The 3D memory device of claim 7 , wherein the gate-to-gate dielectric layers comprise a silicon oxynitride layer and pair of silicon oxide layers, the silicon oxynitride layer being between the pair of silicon oxide layers, and in each of the gate-to-gate dielectric layers, a top surface of the silicon oxynitride layer being fully covered by one of the silicon oxide layers, and a bottom surface of the silicon oxynitride layer being fully covered by another of the silicon oxide layers, along the lateral direction.

19. The 3D memory device of claim 4 , wherein the gate-to-gate dielectric layers comprise a silicon oxynitride layer and pair of silicon oxide layers, the silicon oxynitride layer being between the pair of silicon oxide layers, and in each of the gate-to-gate dielectric layers, a top surface of the silicon oxynitride layer being fully covered by one of the silicon oxide layers, and a bottom surface of the silicon oxynitride layer being fully covered by another of the silicon oxide layers, along a lateral direction, the lateral direction being perpendicular to a vertical direction that the NAND memory string extends.