3D semiconductor apparatus manufactured with a plurality of substrates and method of manufacture thereof

1. A method of forming a semiconductor apparatus, comprising:

forming a first portion of the semiconductor apparatus on a first substrate, the first portion including at least one first semiconductor device;

forming a second portion of the semiconductor apparatus on a second substrate, the second portion including at least one second semiconductor device, the second substrate including a bulk substrate material and a first dielectric layer over the hulk substrate material:

attaching a carrier substrate to the second portion of the semiconductor apparatus, the at least one second semiconductor device being between the carrier substrate and the second substrate;

removing the bulk substrate material from the second substrate;

forming a first wiring layer from the first dielectric layer in the second substrate; and

bonding the first portion and the second portion to form the semiconductor apparatus, the at least one second semiconductor device being stacked above the at least one first semiconductor device along a Z direction that is substantially perpendicular to a substrate plane of the first substrate, and the at least one first semiconductor device and the at least one second semiconductor device being positioned between the carrier substrate and the first substrate.

2. The method of claim 1 , wherein

forming the first portion of the semiconductor apparatus includes forming the first portion on the first substrate of a first wafer; and

forming the second portion of the semiconductor apparatus includes forming the second portion on the second substrate of a second wafer, the second wafer being different from the first wafer and the second substrate being different from the first substrate.

3. The method of claim 2 , wherein

the at least one first semiconductor device includes a first stack of one of NMOS devices and PMOS devices stacked along the Z direction, first channel regions in the first stack being formed by a first epitaxial growth; and

the at least one second semiconductor device includes a second stack of another one of the NMOS devices and the PMOS devices stacked along the Z direction, second channel regions in the second stack being formed by a second epitaxial growth that is different from the first epitaxial growth.

4. The method of claim 2 , wherein

the at least one first semiconductor device includes a first stack of devices stacked along the Z direction, first channel regions in the first stack being formed by a first epitaxial growth, the first stack of device being one of: (a) a stack of NMOS devices, (b) a stack of PMOS devices, and (c) a stack of NMOS and PMOS devices; and

the at least one second semiconductor device includes a second stack of devices stacked along the Z direction, the second stack of device being one of: (a) a stack of NMOS devices, (b) a stack of PMOS devices, and (c) a stack of NMOS and PMOS devices, second channel regions in the second stack being formed by a second epitaxial growth that is different from the first epitaxial growth.

5. The method of claim 1 , wherein

the carrier substrate further includes a second dielectric layer; and

attaching the carrier substrate includes attaching the second dielectric layer in the carrier substrate to the second portion.

6. The method of claim 1 , wherein

forming the second portion of the semiconductor apparatus includes forming a second wiring layer over the at least one second semiconductor device, the at least one second semiconductor device positioned between the second substrate and the second wiring layer; and

attaching the carrier substrate to the second portion includes attaching the carrier substrate to the second wiring layer in the second portion.

7. The method of claim 1 , further comprising:

after bonding the first portion and the second portion to form the semiconductor apparatus, removing the carrier substrate.

8. The method of claim 7 , wherein

forming the first portion of the semiconductor apparatus includes forming a third wiring layer over the at least one first semiconductor device, the at least one first semiconductor device being between the third wiring layer and the first substrate; and

bonding the first portion and the second portion includes bonding the first wiring layer and the third wiring layer.

9. The method of claim 8 , wherein one of the first wiring layer and the third wiring layer includes a power rail.

10. The method of claim 7 , wherein

the at least one first semiconductor device includes a NMOS device;

the at least one second semiconductor device includes a PMOS device;

the carrier substrate further includes a second dielectric layer;

forming the first portion of the semiconductor apparatus includes:

forming a first channel region in the at least one first semiconductor device by a first epitaxial growth; and

forming a third wiring layer over the at least one first semiconductor device, the at least one first semiconductor device positioned between the third wiring layer and the first substrate;

forming the second portion of the semiconductor apparatus further includes:

forming a second channel region in the at least one second semiconductor device by a second epitaxial growth that is different from the first epitaxial growth; and

forming a second wiring layer over the at least one second semiconductor device, the at least one second semiconductor device positioned between the second substrate and the second wiring layer;

attaching the carrier substrate to the second portion includes attaching the second dielectric layer in the carrier substrate to the second wiring layer in the second portion; and

bonding the first portion and the second portion further includes:

positioning the first wiring layer in contact with the third wiring layer to align the at least one first semiconductor device with the at least one second semiconductor device; and

bonding the first portion and the second portion at an interface between the first wiring layer and the third wiring layer.

11. The method of claim 10 , wherein

the first substrate includes a bulk substrate material that is Si; and

forming the second portion of the semiconductor apparatus includes forming the at least one second semiconductor device over a layer of single crystal Si, the second substrate further including the layer of the single crystal Si stacked over the first dielectric layer in the second substrate.

12. The method of claim 10 , wherein

the first substrate includes a bulk substrate material that is Si; and

forming the second portion of the semiconductor apparatus includes forming the at least one second semiconductor device over a layer of a single crystal semiconductor material that is Ge or SiGe, the second substrate further including the layer of the single crystal semiconductor material stacked over the first dielectric layer in the second substrate.

13. The method of claim 10 , wherein

forming the first portion of the semiconductor apparatus includes forming the at least one first semiconductor device over a layer of a first single crystal semiconductor material that is Si or SiC, the first substrate including the layer of the first single crystal semiconductor material stacked over a third dielectric layer; and

forming the second portion of the semiconductor apparatus includes forming the at least one second semiconductor device over a layer of a second single crystal semiconductor material that is Ge or SiGe, the second substrate including the layer of the second single crystal semiconductor material stacked over the first dielectric layer in the second substrate.

14. The method of claim 7 , wherein

the at least one first semiconductor device includes a PMOS device;

the at least one second semiconductor device includes a NMOS device;

the carrier substrate further includes a second dielectric layer;

forming the first portion of the semiconductor apparatus includes forming a first channel region in the at least one first semiconductor device by a first epitaxial growth; and

forming the second portion of the semiconductor apparatus includes:

forming the at least one second semiconductor device over a layer of a single crystal semiconductor material that is Si or SiC, the second substrate including the layer of the single crystal semiconductor material stacked over the first dielectric layer in the second substrate, a second channel region in the at least one second semiconductor device formed by a second epitaxial growth that is different from the first epitaxial growth; and

forming a second wiring layer over the at least one second semiconductor device, the at least one second semiconductor device positioned between the second wiring layer and the second substrate; and

attaching the carrier substrate to the second portion includes attaching the second dielectric layer in the carrier substrate to the second wiring layer in the second portion.

15. The method of claim 14 , wherein

forming the first portion includes forming a third wiring layer over the at least one first semiconductor device, the at least one first semiconductor device positioned between the third wiring layer and the first substrate; and

bonding the first portion and the second portion further includes:

positioning the first wiring layer in contact with the third wiring layer to align the at least one first semiconductor device with the at least one second semiconductor device; and

bonding the first portion and the second portion at an interface between the first wiring layer and the third wiring layer.

16. The method of claim 1 , wherein

the first substrate includes a first layer of a first single crystal semiconductor material stacked on a third dielectric layer; and

forming the first portion of the semiconductor apparatus includes forming the at least one first semiconductor device over the first layer of the first single crystal semiconductor material that is silicon (Si) or silicon carbide (SiC).

17. The method of claim 1 , wherein

the second substrate further includes a second layer of a second single crystal semiconductor material stacked on the first dielectric layer that is on the bulk substrate material; and

forming the second portion of the semiconductor apparatus includes forming the at least one second semiconductor device over the second layer of the second single crystal semiconductor material that is Si, SiC, germanium (Ge), or silicone germanium (SiGe).

18. The method of claim 1 , wherein

the at least one first semiconductor device includes one of a NMOS device and a PMOS device;

the at least one second semiconductor device includes another one of the NMOS device and the PMOS device;

forming the first portion includes forming a first channel region in the at least one first semiconductor device by a first epitaxial growth; and

formingg the second portion includes forming a second channel region in the at least one second semiconductor device by a second epitaxial growth that is different from the first epitaxial growth.

19. The method of claim 1 , wherein

forming the first portion of the semiconductor apparatus includes forming the first portion on the first substrate of a first wafer; and

forming the second portion of the semiconductor apparatus includes forming the second portion on the second substrate of a second wafer, the second wafer being different from the first wafer.

20. The method of claim 19 , wherein

the at least one first semiconductor device includes a first stack of one of NMOS devices and PMOS devices stacked along the Z direction, first channel regions in the first stack being formed by a first epitaxial growth; and

the at least one second semiconductor device includes a second stack of another one of the NMOS devices and the PMOS devices stacked along the Z direction, second channel regions in the second stack being formed by a second epitaxial growth that is different from the first epitaxial growth.