IP Library Granted Patent US 11,616,014
Granted Patent B2
US 11,616,014 · App. 16/638,907 · Granted Mar 28, 2023

Peripheral inductors

Inventors: Kevin L. Lin (Beaverton, OR); Paul B. Fischer (Portland, OR)
Assignee: Intel Corporation
H01L23/5227H01F27/06H01L23/564H01L23/585H01L24/16H01L28/10H01F41/00H01L2224/16227H01L2924/1206H01L2924/14252
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Quick Facts
Patent No.
US 11,616,014
App. No.
16/638,907
Granted
Mar 28, 2023
Kind
B2
Abstract

Disclosed herein are peripheral inductors for integrated circuits (ICs), as well as related methods and devices. In some embodiments, an IC device may include a die having an inductor extending around at least a portion of a periphery of the die.

Claims (30)

1. An integrated circuit (IC) device comprising a die, the die comprising:

an inductor extending around at least a portion of a periphery of the die, the inductor having a first end and a second end;

an insulating material that separates the first end of the inductor from the second end of the inductor; and

circuitry in an interior of the inductor, the circuitry comprising a plurality of transistors, wherein the first end of the inductor is electrically coupled to the circuitry in the interior of the inductor, and a footprint of the circuitry is inside a footprint of the inductor.

2. The IC device of claim 1 , wherein the inductor is included in a metallization stack of the die.

3. The IC device of claim 2 , wherein the inductor has the first end in a first layer of the metallization stack, the inductor has the second end in a second layer of the metallization stack, and the first layer is different from the second layer.

4. The IC device of claim 2 , wherein the first end of the inductor spans multiple interconnect layers of the metallization stack.

5. The IC device of claim 1 , wherein the inductor and the insulating material provide a hermetic seal for the die.

6. The IC device of claim 1 , wherein the circuitry includes a buck-boost converter.

7. The IC device of claim 1 , wherein the second end of the inductor is electrically coupled to the circuitry in the interior of the inductor.

8. The IC device of claim 1 , wherein the die further includes conductive contacts, and the first end of the inductor is electrically coupled to a conductive contact.

9. A die, comprising:

a conductive structure in a periphery of the die, the conductive structure having a first end and a second end, wherein the conductive structure is proximate to at least two edges of the die, and the conductive structure does not form a closed loop;

an insulating material that separates the first end of the conductive structure from the second end of the conductive structure; and

circuitry in an interior of the conductive structure, the circuitry comprising a plurality of transistors, wherein the first end of the conductive structure is electrically coupled to the circuitry in the interior of the conductive structure, and a footprint of the circuitry is inside a footprint of the conductive structure.

10. The die of claim 9 , wherein the insulating material includes a nitride.

11. The die of claim 9 , wherein the conductive structure and the insulating material provide a hermetic seal for the die.

12. The die of claim 9 , further comprising:

a guard ring extending around the periphery of the die, wherein the conductive structure is in an interior of the guard ring.

13. The die of claim 12 , wherein the guard ring provides a hermetic seal for the die.

14. The die of claim 9 , further comprising:

conductive contacts at a face of the die, wherein the second end of the conductive structure is electrically coupled to a conductive contact.

15. A computing device, comprising:

an integrated circuit (IC) package, wherein the IC package includes a die, and the die includes an inductor extending around at least a portion of a periphery of the die, the inductor having a first end and a second end, and the die further includes:

an insulating material that separates the first end of the inductor from the second end of the inductor, and

circuitry in an interior of the inductor, the circuitry comprising a plurality of transistors, wherein the first end of the inductor is electrically coupled to the circuitry in the interior of the inductor, and a footprint of the circuitry is inside a footprint of the inductor; and

a circuit board, wherein the IC package is coupled to the circuit board.

16. The computing device of claim 15 , wherein the IC package is a flip chip package.

17. The computing device of claim 15 , further comprising:

a wireless communications device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072792/0592 →
Continuity (1)
Related Publication 20200365510A1 · Nov 19, 2020