IP Library › Granted Patent US 11,616,020

Granted Patent B2

US 11,616,020 · App. 17/381,449 · Granted Mar 28, 2023

Power distribution network for 3D logic and memory

Inventors: Lars Liebmann (Mechanicville, NY); Jeffrey Smith (Clifton Park, NY); Anton J. deVilliers (Clifton Park, NY); Kandabara Tapily (Mechanicville, NY)

Assignee: Tokyo Electron Limited

H01L23/5286 H01L25/0657 H01L27/1104 H01L29/0847

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Quick Facts

Patent No.: US 11,616,020
App. No.: 17/381,449
Granted: Mar 28, 2023
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A semiconductor device includes a transistor stack. The transistor stack has a plurality of transistors that are stacked over a substrate. Each of the plurality of transistors includes a channel region stacked over the substrate and extending in a direction parallel to the substrate, a gate structure stacked over the substrate and surrounding the channel region of each of the plurality of transistors, and source/drain (S/D) regions stacked over the substrate and further positioned at two ends of the channel region of each of the plurality of transistors. The semiconductor device also includes one or more conductive planes formed over the substrate. The one or more conductive planes are positioned adjacent to the transistor stack, span a height of the transistor stack, and are electrically coupled to the transistor stack.

Claims (40)

1. A semiconductor device, comprising:

a transistor stack having a plurality of transistors that are stacked over a substrate, wherein each of the plurality of transistors includes a channel region stacked over the substrate and extending in a direction parallel to the substrate, a gate structure stacked over the substrate and surrounding the channel region of each of the plurality of transistors, and source/drain (S/D) regions stacked over the substrate and further positioned at two ends of the channel region of each of the plurality of transistors; and

one or more conductive planes formed over the substrate, the one or more conductive planes being positioned adjacent to the transistor stack, spanning a height of the transistor stack and being electrically coupled to the transistor stack.

2. The semiconductor device of claim 1 , further comprising:

gate electrodes stacked over the substrate and electrically coupled to the gate structures of the plurality of transistors, and

S/D local interconnects stacked over the substrate and electrically coupled to the S/D regions of the plurality of transistors.

3. The semiconductor device of claim 1 , further comprising:

a plurality of power rails that are positioned below the transistor stack, wherein each of the one or more conductive planes is positioned over and extends along a respective power rail of the plurality of power rails so as to form a continuous connection.

4. The semiconductor device of claim 1 , further comprising:

a plurality of power rails that are positioned below the transistor stack, wherein each of the one or more conductive planes is positioned over and across two or more power rails of the plurality of power rails so as to form two or more connection points.

5. The semiconductor device of claim 3 , wherein the one or more conductive planes comprise a continuous lateral structure to draw power from the plurality of power rails into the transistor stack.

6. The semiconductor device of claim 3 , wherein the one or more conductive planes comprise a piecewise interrupted structure with one or more channels being arranged therein, the piecewise interrupted structure being configured to create a conductive path from the plurality of power rails into the transistor stack.

7. The semiconductor device of claim 1 , further comprising:

a plurality of power rails, the plurality of power rails being positioned over the one or more conductive planes, each of the one or more conductive planes being positioned along a respective power rail of the plurality of power rails so as to form a continuous connection.

8. The semiconductor device of claim 1 , wherein one or more of the plurality of transistors are electrically coupled to the one or more conductive planes through the S/D regions of the one or more of the plurality of transistors.

9. The semiconductor device of claim 2 , further comprising:

a plurality of vertical contacts formed in a direction perpendicular to the substrate and electrically coupled to the S/D local interconnects of the plurality of transistors, at least one of the plurality of vertical contacts being electrically coupled to an output signal.

10. A method of forming a semiconductor device, comprising:

forming a transistor stack including a plurality of transistors that are stacked over a substrate, wherein each of the plurality of transistors includes a channel region stacked over the substrate and extending in a direction parallel to the substrate, a gate structure stacked over the substrate and surrounding the channel region of each of the plurality of transistors, source/drain (S/D) regions stacked over the substrate and further positioned at two ends of the channel region of each of the plurality of transistors,

forming gate electrodes that are stacked over the substrate and electrically coupled to the gate structures of the plurality of transistors, and forming S/D local interconnects that are stacked over the substrate and electrically coupled to the S/D regions of the plurality of transistors; and

forming one or more conductive planes over the substrate, the one or more conductive planes being positioned adjacent to the transistor stack, spanning a height of the transistor stack and being electrically coupled to the transistor stack.

11. The method of claim 10 , further comprising:

forming a plurality of power rails, the plurality of power rails being positioned below the transistor stack, each of the one or more conductive planes extending along a respective power rail of the plurality of power rails so as to form a continuous connection.

12. The method of claim 10 , further comprising:

forming a plurality of power rails, the plurality of power rails being positioned below the transistor stack, each of the one or more conductive planes being positioned over and across two or more power rails of the plurality of power rails so as to form two or more connection points.

13. The method of claim 10 , further comprising:

forming a plurality of power rails, the plurality of power rails being positioned over the one or more conductive planes, each of the plurality of power rails extending along a respective power rail of the plurality of power rails so as to form a continuous connection.

14. The method of claim 10 , wherein the one or more conductive planes comprises a continuous lateral structure to draw power from a plurality of power rails into the transistor stack.

15. The method of claim 10 , wherein the one or more conductive planes comprises a piecewise interrupted structure that leaves channels and draws power from a plurality of power rails into the transistor stack.

16. The method of claim 10 , wherein one or more of the plurality of transistors are electrically coupled to the one or more conductive planes through the S/D regions of the one or more of the plurality of transistors.

17. The method of claim 10 , further comprising:

forming a plurality of vertical contacts that are positioned in a direction perpendicular to the substrate and electrically coupled to the S/D local interconnects of the plurality of transistors, at least one of the plurality of vertical contacts being electrically coupled to an output signal.

18. A semiconductor device, comprising:

a plurality of transistors stacked over a substrate, wherein each of the plurality of transistors includes a channel region stacked over the substrate and extending in a direction parallel to the substrate, a gate structure stacked over the substrate and surrounding the channel region of each of the plurality of transistors, and source/drain (S/D) regions stacked over the substrate and further positioned at two ends of the channel region of each of the plurality of transistors;

a plurality of gate electrodes that are stacked over the substrate and electrically coupled to the gate structures of the plurality of transistors;

a plurality of S/D local interconnects that are stacked over the substrate and electrically coupled to the S/D regions of the plurality of transistors;

one or more conductive planes formed over the substrate, the one or more conductive planes being positioned adjacent to the plurality of transistors, spanning a height of the plurality of transistors and being electrically coupled to the plurality of transistors; and

a plurality of power rails that are positioned over the substrate and electrically coupled to the one or more conductive planes.

19. The semiconductor device of claim 18 , wherein the plurality of power rails are positioned over the one or more conductive planes, each of the plurality of power rails extending along a respective power rail of the plurality of power rails so as to form a continuous connection.

20. The semiconductor device of claim 18 , wherein the plurality of power rails are positioned below the one or more conductive planes, each of the one or more conductive planes either being positioned over and extending along a respective power rail of the plurality of power rails so as to form a continuous connection, or being positioned over and across two or more power rails of the plurality of power rails so as to form two or more connection points.

Continuity (3)

Continuation 16560544 · Sep 4, 2019

Provisional Application 62727098 · Sep 5, 2018

Related Publication 20210351132A1 · Nov 11, 2021