IP Library Granted Patent US 11,616,064
Granted Patent B2
US 11,616,064 · App. 17/019,956 · Granted Mar 28, 2023

Semiconductor structure

Inventor: Yong Li (Shanghai, CN)
Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; SMIC New Technology Research and Development (Shanghai) Corporation
H01L27/0924H01L21/823431H01L21/823821H01L29/41791H01L29/66795H01L29/785H01L29/7848H01L21/845
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,616,064
App. No.
17/019,956
Granted
Mar 28, 2023
Kind
B2
Abstract

A semiconductor structure is provided. The semiconductor structure includes a base substrate including a semiconductor substrate having a PMOS region and an NMOS region and a plurality of fins on the semiconductor substrate, a gate layer across the plurality of fins by covering portions of top and sidewall surfaces of the fins, a P-type doped epitaxial layer formed in the fins at both sides of the gate layer in the PMOS region, an N-type doped epitaxial layer formed in the fins at both sides of the gate layer in the NMOS region, and an N-region mask layer formed on sidewall surfaces of the N-type doped epitaxial layer and covering the P-type doped epitaxial layer. A portion of the N-type doped epitaxial layer exposed by the N-region mask layer is processed by an N-type dopant segregated Schottky doping process.

Claims (32)

1. A semiconductor structure, comprising:

a base substrate including a semiconductor substrate having a PMOS region and an NMOS region and a plurality of fins on the semiconductor substrate;

a gate layer across the plurality of fins by covering portions of top and sidewall surfaces of the fins;

shallow trench isolation structures formed on the semiconductor substrate, top surfaces of the shallow trench isolation structures are lower than top surfaces of the plurality of fins;

a P-type doped epitaxial layer formed in the fins at both sides of the gate layer in the PMOS region;

an N-type doped epitaxial layer formed in the fins at both sides of the gate layer in the NMOS region;

an interlayer dielectric layer formed over the semiconductor substrate exposing the P-type doped epitaxial layer and the N-type doped epitaxial layer; and

a metal silicide layer formed on a portion of the P-type doped epitaxial layer and a portion of the N-type doped epitaxial layer not covered by the interlayer dielectric layer;

wherein:

a portion of the N-type doped epitaxial layer exposed by an N-region mask layer is processed by an N-type dopant segregated Schottky doping process to form a doped region on top of a remaining portion of the N-type doped epitaxial layer;

along a direction perpendicular to a length direction of the fin, a width of a bottom of the N-type epitaxial layer is greater than a width of the fin, and a width of a bottom of the P-type epitaxial layer is greater than the width of the fin; and

a portion of the metal silicide layer is formed between the bottom of the N-type epitaxial layer and the top surfaces of the shallow trench isolation structures, another portion of the metal silicide layer is formed between the bottom of the P-type epitaxial layer and the top surfaces of the shallow trench isolation structures.

2. The semiconductor structure according to claim 1 , wherein:

doping ions of the N-type dopant segregated Schottky doping process include at least one of P ions, As ions and Sb ions.

3. The semiconductor structure according to claim 2 , wherein:

the N-type dopant segregated Schottky (DSS) doping process is an ion implantation process;

an implanting energy of the ion implantation process is in a range of approximately 100 eV-1 keV; and

an implanting dosage of the ion implantation process is in a range of approximately 1E14 atom/cm 2 -1E16 atom/cm 2 .

4. The semiconductor structure according to claim 1 , wherein:

a height difference between top surfaces of the fins under the N-type doped epitaxial layer and top surfaces of the shallow trench isolation structures is in range approximately from −3 nm to 3 nm.

5. The semiconductor structure according to claim 1 , wherein:

the N-region mask layer is made of one of silicon nitride, silicon oxide, boron nitride, silicon carbonitride, silicon boron oxycarbonitride, and silicon oxynitride.

6. The semiconductor structure according to claim 1 , wherein:

a height difference between top surfaces of the fins under the P-type doped epitaxial layer and top surfaces of the shallow trench isolation structures is in range approximately from −3 nm to 3 nm.

7. The semiconductor structure according to claim 1 , further comprising:

a contact plug, electrically contacting with the P-type doped epitaxial layer and the N-type doped epitaxial layer.

8. The semiconductor structure according to claim 7 , further comprising:

a metal layer formed on the metal silicide layer and the semiconductor substrate; and

a barrier layer between the metal layer and the contact plug.

9. The semiconductor structure according to claim 1 , wherein:

a top portion of the N-type epitaxial layer is doped with certain doping ions.

10. The semiconductor structure according to claim 1 , wherein doping ions of the N-type dopant segregated Schottky doping process include at least one of P ions or As ions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2025
From: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION; SMIC NEW TECHNOLOGY RESEARCH AND DEVELOPMENT (SHANGHAI) CORPORATION
To: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Reel/Frame 072716/0862 →
Priority Claims (1)
CN 201710735050.8 · Aug 24, 2017 · national
Continuity (2)
Division 16106222 · Aug 21, 2018
Related Publication 20200411519A1 · Dec 31, 2020
Cited By (1)
US 12,666,709