Three-dimensional memory arrays, and methods of forming the same
An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.
1. A method, comprising:
forming a first dielectric material and a storage element material over a semiconductor material;
forming a first plurality of openings in the first dielectric material and the storage element material;
removing portions of the storage element material adjacent the first plurality of openings;
forming a first electrode material in an area from which the portions of the storage element material were removed;
forming a sense line material in the first plurality of openings adjacent the first electrode material;
forming a second plurality of openings in the first dielectric material and the storage element material;
removing portions of the storage element material adjacent the second plurality of openings;
forming a second electrode material in an area from which the portions of the storage element material adjacent the second plurality of openings were removed;
forming an access line material in the second plurality of openings adjacent the second electrode material;
removing a portion of the access line material from the second plurality of openings;
forming a second dielectric material in an area from which the portion of the access line material was removed; and
forming a horizontal sense line material over the sense line material to connect the sense line material formed in the first plurality of openings.
2. The method of claim 1 , further comprising alternatively forming the first dielectric material and the storage element material over each other.
3. The method of claim 1 , further comprising forming the first and second plurality of openings using a non-selective etch.
4. The method of claim 1 , further comprising removing the portions of the storage element material adjacent the first and second plurality of openings using a selective etch.
5. The method of claim 1 , further comprising removing more storage element material adjacent the second plurality of openings than storage element material adjacent the first plurality of openings.
6. The method of claim 5 , further comprising removing a portion of the first electrode material and the second electrode material.
7. The method of claim 1 , further comprising forming the sense line material using atomic layer deposition (ALD).
8. The method of claim 1 , wherein the sense line material and the access line material are a same material.
9. The method of claim 1 , wherein the first and second dielectric materials are different materials.
10. The method of claim 1 , further comprising forming the second plurality of openings adjacent to the first plurality of openings.
11. A method, comprising:
forming a first horizontal sense line material in a substrate material;
forming a first dielectric material and a storage element material over the horizontal sense line material;
forming a first plurality of openings in the first dielectric material and the storage element material;
removing portions of the storage element material adjacent the first plurality of openings;
forming a first electrode material in an area from which the storage element material was removed;
forming a sense line material in the first plurality of openings;
forming a second plurality of openings in the first dielectric material and the storage element material;
removing portions of the storage element material adjacent the second plurality of openings;
forming a second electrode material in an area from which the portions of the storage element material adjacent the second plurality of openings were removed;
forming an access line material in the second plurality of openings adjacent the second electrode material;
removing a portion of the access line material from the second plurality of openings;
forming a second dielectric material in an area from which the access line material was removed; and
forming a second horizontal sense line material over the sense line material to connect the sense line material formed in the first plurality of openings.
12. The method of claim 11 , further comprising forming the second dielectric material in the second plurality of openings.
13. The method of claim 11 , further comprising forming the access line material in the first plurality of openings and forming the sense line material in the second plurality of openings.
14. The method of claim 13 , further comprising forming a horizontal access line material over the access line material to connect the access line material formed in the first plurality of openings.
15. A method, comprising:
forming a three-dimensional (3D) memory array by:
forming a sense line that includes vertical portions and horizontal portions; and
forming a plurality of vertical stacks, wherein forming each respective one of the vertical stacks includes:
forming a different respective vertical portion of the sense line, wherein the different respective vertical portion of the sense line of each respective vertical stack is in contact with multiple layers of its respective vertical stack;
forming a first memory cell coupled to the different respective vertical portion of the sense line;
forming a second memory cell coupled to the different respective vertical portion of the sense line;
forming a first access line coupled to the first memory cell, wherein the first access line is perpendicular to the different respective vertical portion of the sense line; and
forming a second access line coupled to the second memory cell, wherein the second access line is perpendicular to the different respective vertical portion of the sense line.
16. The method of claim 15 , further comprising forming a third memory cell coupled to the different respective vertical portion of the sense line and a fourth memory cell coupled to the different respective vertical portion of the sense line.
17. The method of claim 16 , further comprising forming the third memory cell on a same side of the different respective vertical portion of the sense line as the first memory cell.
18. The method of claim 16 , further comprising forming the fourth memory cell on a same side of the different respective vertical portion of the sense line as the second memory cell.
19. The method of claim 16 , further comprising forming the third memory cell and the fourth memory cell on opposing sides of the different respective vertical portion of the sense line.
20. The method of claim 16 , further comprising forming a third access line coupled to the third memory cell and forming a fourth access line coupled to the fourth memory cell, wherein the third access line and the fourth access line are perpendicular to the different respective vertical portion of the sense line.