Semiconductor device, ferroelectric capacitor and laminated structure
View Patent ↗A semiconductor device includes a substrate, a gate stack over the substrate, a channel layer over the gate stack, and a source/drain electrode. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The source/drain electrode is formed on the channel layer and disposed on sides of the gate stack.
1. A semiconductor device including:
a substrate;
a gate stack over the substrate, wherein the gate stack includes:
a metal gate electrode;
a ferroelectric layer; and
a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode, wherein the semiconducting oxide layer includes SrRuO 3 , InGaZnO (IGZO) or LaSrMnO;
a channel layer over the gate stack; and
a source/drain electrode formed on the channel layer and disposed on sides of the gate stack.
2. The semiconductor device of claim 1 , wherein the semiconducting oxide layer has a thickness between approximately 1 μm and approximately 30 μm.
3. The semiconductor device of claim 1 , wherein the ferroelectric layer includes a ferroelectric material including HfSiOx, HfZrOx, Al 2 O 3 , TiO 2 , LaO x , BaSrTiO x (BST), PbZr x Ti y O z (PZT), BiFeO 3 (BFO) or (Pb v La w )(Zr x Ti y )O z (PLZT), or a combination thereof.
4. The semiconductor device of claim 1 , wherein the source electrode and the drain electrode are separated by an insulating structure.
5. The semiconductor device of claim 1 , wherein the source electrode and the drain electrode includes metallic materials.
6. The semiconductor device of claim 1 , further comprising a high-k dielectric layer disposed between the ferroelectric layer and the channel layer.
7. The semiconductor device of claim 1 , wherein the ferroelectric layer is over the semiconducting oxide layer.
8. A ferroelectric capacitor, including:
a first electrode layer,
a second electrode layer;
a ferroelectric layer between the first electrode layer and the second electrode layer,
a first semiconducting oxide layer disposed between the ferroelectric layer and the first electrode layer, and
a second semiconducting oxide layer disposed between the ferroelectric layer and the second electrode layer,
wherein the first electrode layer has the same material as the first semiconducting oxide layer, and the second electrode layer has the same material as the second semiconducting oxide layer.
9. The ferroelectric capacitor of claim 8 , wherein the first semiconducting oxide layer and the second semiconducting oxide layer independently includes SrRuO 3 , InGaZnO (IGZO) or LaSrMnO.
10. The ferroelectric capacitor of claim 8 , wherein the second electrode layer has the same material as the first semiconducting oxide layer.
11. The ferroelectric capacitor of claim 8 , wherein the ferroelectric layer includes a ferroelectric material including HfSiOx, HfZrOx, Al 2 O 3 , TiO 2 , LaO x , BaSrTiO x , (BST), PbZr x Ti y O z (PZT), BiFeO 3 (BFO) or (Pb v La w )(Zr x Ti y )O z (PLZT), or a combination thereof.
12. The ferroelectric capacitor of claim 8 , wherein the first semiconducting oxide layer includes SrRuO 3 , InGaZnO (IGZO) or LaSrMnO.
13. The ferroelectric capacitor of claim 8 , wherein the first semiconducting oxide layer has a thickness between approximately 1 μm and approximately 30 μm.
14. The ferroelectric capacitor of claim 8 , wherein the ferroelectric layer is separated from at least the first electrode layer or the second electrode layer.
15. The ferroelectric capacitor of claim 8 , wherein the ferroelectric layer is disposed between the first semiconducting oxide electrode layer and the second semiconducting oxide electrode layer.
16. A laminated structure including:
a ferroelectric layer;
a first electrode layer over the ferroelectric layer; and
a second electrode layer; wherein the ferroelectric layer is between the first electrode layer and the second electrode layer,
a semiconducting oxide layer, disposed between the ferroelectric layer and the first electrode layer,
wherein the second electrode layer has the same material as the semiconducting oxide layer.
17. The laminated structure of claim 16 , wherein the semiconducting oxide layer includes SrRuO 3 , InGaZnO (IGZO) or LaSrMnO.
18. The laminated structure of claim 16 , wherein the semiconducting oxide layer has a thickness between approximately 1 μm and approximately 30 μm.
19. The laminated structure of claim 16 , further including:
a channel layer; and
a source/drain electrode, wherein the channel layer is disposed between the source/drain electrode and the ferroelectric layer.
20. The laminated structure of claim 16 , wherein the ferroelectric layer and the semiconducting oxide layer are between the first electrode layer and the second electrode layer.