Semiconductor device, ferroelectric capacitor and laminated structure
View Patent ↗A device includes a gate stack and a channel layer over the gate stack. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The semiconducting oxide layer has a thickness between approximately 1 μm and approximately 30 μm.
1. A device, comprising:
a gate stack including:
a metal gate electrode;
a ferroelectric layer, wherein the ferroelectric layer includes a ferroelectric material including HfSiO x , HfZrO x , Al 2 O 3 , TiO 2 , LaOx, BaSrTiO x (BST), PbZr x Ti y O z (PZT), BiFeO 3 (BFO) or (Pb y La w )(Zr x Ti y )O z (PLZT), or a combination thereof;
a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode, wherein the semiconducting oxide layer has a thickness between approximately 1 μm and approximately 30 μm; and
a channel layer over the gate stack.
2. The device of claim 1 , wherein the semiconducting oxide layer includes SrRuO 3 , InGaZnO (IGZO) or LaSrMnO.
3. The device of claim 1 , further comprising a high-k dielectric layer disposed between the ferroelectric layer and the channel layer.
4. The device of claim 1 , wherein the ferroelectric layer is over the semiconducting oxide layer.
5. The device of claim 1 , wherein the ferroelectric layer has a thickness between approximately 5 nm and approximately 20 nm.
6. A device, comprising:
a ferroelectric capacitor, including:
a first semiconducting oxide electrode layer,
a second semiconducting oxide electrode layer;
a ferroelectric layer between the first semiconducting oxide electrode layer and the second semiconducting oxide electrode layer, wherein the ferroelectric layer includes a ferroelectric material including HfSiO x , HfZrO x , Al 2 O 3 , TiO 2 , LaO x , BaSrTiO x (BST), PbZr x Ti y O z (PZT), BiFeO 3 (BFO) or (Pb y La w )(Zr x Ti y )O z (PLZT), or a combination thereof; and
a first semiconducting oxide layer disposed between the ferroelectric layer and the second semiconducting oxide electrode layer,
wherein the first semiconducting oxide electrode layer has a thickness between approximately 1 μm and approximately 30 μm.
7. The device of claim 6 , wherein the second semiconducting oxide electrode layer includes SrRuO 3 , InGaZnO (IGZO) or LaSrMnO.
8. The device of claim 6 , wherein the second semiconducting oxide electrode layer has the same material as the first semiconducting oxide electrode layer.
9. The device of claim 8 , wherein the first semiconducting oxide electrode layer and second semiconducting oxide electrode layer includes SrRuO 3 , InGaZnO (IGZO) or LaSrMnO.
10. The device of claim 6 , wherein the first semiconducting oxide electrode layer includes SrRuO 3 , InGaZnO (IGZO) or LaSrMnO.
11. The device of claim 6 , wherein the ferroelectric layer is separated from at least the first semiconducting oxide electrode layer or the second semiconducting oxide electrode layer.
12. The device of claim 6 , wherein the ferroelectric layer has a thickness between approximately 5 nm and approximately 20 nm.
13. A device, comprising:
a laminated structure including:
a ferroelectric layer, wherein the ferroelectric layer includes a ferroelectric material including HfSiO x , HfZrO x , Al 2 O 3 , TiO 2 , LaO x , BaSrTiO x (BST), PbZr x Ti y O z (PZT), BiFeO 3 (BFO) or (Pb y La w )(Zr x Ti y )O z (PLZT), or a combination thereof;
an electrode layer over the ferroelectric layer;
a semiconducting oxide electrode layer; wherein the ferroelectric layer is between the electrode layer and the semiconducting oxide electrode layer,
wherein the semiconducting oxide electrode layer has a thickness between approximately 1 μm and approximately 30 μm.
14. The device of claim 13 , wherein the semiconducting oxide electrode layer includes SrRuO 3 , InGaZnO (IGZO) or LaSrMnO.
15. The device of claim 13 , further including:
a channel layer; and
a source/drain electrode, wherein the channel layer is disposed between the source/drain electrode and the ferroelectric layer.
16. The device of claim 15 , further comprising a high-k dielectric layer disposed between the ferroelectric layer and the channel layer.
17. The device of claim 15 , wherein the source electrode and the drain electrode are separated by an insulating structure.
18. The device of claim 15 , further including a substrate and a buffer layer over the substrate, wherein the source electrode and the drain electrode are disposed over the buffer layer.
19. The device of claim 13 , wherein the ferroelectric layer is over the semiconducting oxide electrode layer.
20. The device of claim 13 , wherein the ferroelectric layer is separated from the electrode layer.